LayerscapeのトピックRe: Debug Access levels for SDC in LS1046A

Debug Access levels for SDC in LS1046A

Faizanbaig — Thu, 22 Jun 2023 08:55:26 GMT

Hi,

I want to have clarification regarding Secure debug access Level 3 .

My doubt is:

If I just set(not permanently fuse) 0x100 in OEM Security Policy Register 1 (SFP_OSPR1) debug access level 3, what will be the effect on SDC?

Can I use SDC access level 3 in development (Lab) environment ?

Any help would be appreciated.

Thanks in advance,
Faizan

@chitra_amzarewa

Re: Debug Access levels for SDC in LS1046A

Faizanbaig — Wed, 28 Jun 2023 10:23:28 GMT

Just reminding for any suggestions..
Can we switch between levels on each power cycle in lab environment?
Any help or suggestions on this?

Re: Debug Access levels for SDC in LS1046A

khushbur — Thu, 29 Jun 2023 09:29:40 GMT

Hi @Faizanbaig

All the fuse are blown once bit. Once you burn a fuse bit from b'0 to a b'1, you cannot turn a fuse b'1 back to a b'0. That is why the
OEM Security Policy Register 1 (SFP_OSPR1), bit 29–31 DBLEV
000 Open: Debug portals are enabled unconditionally.
001 Conditionally closed via challenge response, without notification.
01x 01x: Conditionally closed via challenge response, with notification.
1xx 1xx: Closed. All debug portals are disabled.
instead of use decimal value 1,2,3,4.

Thanks

Khushbu

Re: Debug Access levels for SDC in LS1046A

Faizanbaig — Thu, 29 Jun 2023 09:40:46 GMT

My question is "can we set debug levels without blowing the fuses just like SRKH mirror register"?

Re: Debug Access levels for SDC in LS1046A

KatheAshokkumar — Wed, 10 Jan 2024 14:30:35 GMT

Hi Team,

Is there any update on above query ?

Regards,
Ashok

Re: Debug Access levels for SDC in LS1046A

Faizanbaig — Wed, 24 Jan 2024 06:25:48 GMT

Hi,

No updates

Regards,
Faizan