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    <title>topic Re: LS1046A PCIe x2 Lane assignment in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1046A-PCIe-x2-Lane-assignment/m-p/1790543#M13882</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Lane 0 - C&lt;/P&gt;
&lt;P&gt;Lane 1 - D&lt;/P&gt;
&lt;P&gt;Have a nice day!!&lt;/P&gt;</description>
    <pubDate>Wed, 17 Jan 2024 20:38:56 GMT</pubDate>
    <dc:creator>Oswalag</dc:creator>
    <dc:date>2024-01-17T20:38:56Z</dc:date>
    <item>
      <title>LS1046A PCIe x2 Lane assignment</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-PCIe-x2-Lane-assignment/m-p/1788850#M13876</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We are building a custom board and need a PCIe link (Gen1, 2.5Gbps)) which can support either PCIe x1 or PCIe x2.&lt;/P&gt;&lt;P&gt;From the LS1046A Reference Manual (rev.3, 08/2021), in Table 31-2, we can configure PCIe.3 x1 to use:&lt;/P&gt;&lt;P&gt;&amp;nbsp; - SERDES C (RX2/TX2) with SRDS_PRTCL_S2= 5559, 0559 or 5A59&lt;/P&gt;&lt;P&gt;&amp;nbsp; - SERDES C (RX3/TX3) with SRDS_PRTCL_S2= 5506, 0506 or 5A06&lt;/P&gt;&lt;P&gt;Which means that for a x1 Link, we can connect either C or D to lane 0 of the other device.&lt;/P&gt;&lt;P&gt;In PCIe x2, neither the other device&amp;nbsp; nor the LS1046A supports lane reversal. In the LS1046ARM (section 25.6.1.2, Table 25.6 and below), it states that: "The x2 controller does not support lane reversal." and the table says that for x2 link Lane 0 is 0 and Lane 1 is 1.&lt;/P&gt;&lt;P&gt;So if we use&amp;nbsp;SRDS_PRTCL_S2= 5577 for PCIe.3 x2, which of C or D is Lane 0 to be connected to the Lane 0 of the other device ?&lt;/P&gt;</description>
      <pubDate>Mon, 15 Jan 2024 15:32:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-PCIe-x2-Lane-assignment/m-p/1788850#M13876</guid>
      <dc:creator>GyM</dc:creator>
      <dc:date>2024-01-15T15:32:24Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A PCIe x2 Lane assignment</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-PCIe-x2-Lane-assignment/m-p/1790543#M13882</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Lane 0 - C&lt;/P&gt;
&lt;P&gt;Lane 1 - D&lt;/P&gt;
&lt;P&gt;Have a nice day!!&lt;/P&gt;</description>
      <pubDate>Wed, 17 Jan 2024 20:38:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-PCIe-x2-Lane-assignment/m-p/1790543#M13882</guid>
      <dc:creator>Oswalag</dc:creator>
      <dc:date>2024-01-17T20:38:56Z</dc:date>
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