LayerscapeのトピックRe: LS1046A IFC Async NAND interface

LS1046A IFC Async NAND interface

Daves_Garage — Tue, 24 Jan 2023 23:07:59 GMT

Hi, I'm looking for an explanation for the base address of NAND being used in u-boot for both the RDB and FRWY development boards. The base address is 0x7e800000, and I can't seem to figure out why this is the case.

If I added an additional NAND chip, using CS1 instead of CS0, would I increase this size by the size of the chip?

Would I use the same address?

How was this address derived?

Any pointers are greatly appreciated. Thank you in advance.

Re: LS1046A IFC Async NAND interface

Daves_Garage — Wed, 25 Jan 2023 15:35:24 GMT

Ok, this address refers to the SRAM buffer being used by the IFC when you're talking to NAND. It has a maximum size (I think it's 0x10000), and since the buffer (which is memory mapped I believe also) is used for all NAND devices (you can't access more than one at a time), the address is the same for all...

I still haven't figured out where the address came from... although, I have come to realize the reference manual is pretty big

Still looking for help understanding how this address is known...

Anyone?

Re: LS1046A IFC Async NAND interface

Hector_Villarruel — Wed, 25 Jan 2023 20:37:27 GMT

Hello Daves Garage,

This post is to inform you that I'm working on your case,

Kindly give some time and I will update you,

I'll keep you informed of the progress.

Best Regards,

Hector Villarruel

Re: LS1046A IFC Async NAND interface

Daves_Garage — Wed, 25 Jan 2023 20:50:02 GMT

Hi Hector, I've done a bit more reading and experimenting by modifying the base address on a couple of chips on my custom board, and I think I understand the solution now, namely: The address doesn't mean a thing...

Regarding SRAM buffer for NAND devices
see section 22.5.5 SRAM buffer of the LS1046A Reference Manual, Rev. 3, 08/2021

Buffer RAM consists of 16KB (16,384 bytes) or 0x4000 bytes
This RAM is shared as read/write memory for ALL devices (since they can’t be accessed at the same time)
The base address for the device is simply a way to differentiate them from each other, however address spacing must account for the buffer size, since it is shared and merely remapped for each device.
Base address of 0x7E800000 is arbitrary
U-boot software works with NAND1 and NAND2 base addresses set as follows:

#define CONFIG_SYS_NAND_BASE 0x60000000 #define CONFIG_SYS_NAND_BASE2 0x60004000

What are your thoughts?

Re: LS1046A IFC Async NAND interface

Daves_Garage — Thu, 26 Jan 2023 23:51:32 GMT

SUPER IMPORTANT POINT ABOUT THIS INTERFACE...

The bus between the NAND chip and the LS1046A IFC is bitwise reversed... Yes, AD0 connects to AD7 on your NAND part, AD1 to AD6, and so on... In the 2500+ page reference manual, there are actually 3 places that describe this bitwise reversal, and they are in picture form, not words.

(see figures 22-58, 22-59, and 22-60) It looks like this:

Something you could easily over look, because lets face it; when I think about connecting address and data busses, I go with 0 goes to 0, 1 goes to 1, etc...

I'm thinking this was a mistake originally; wonder what the first edition of the reference manual looks like.

Anyway, be careful, or you'll find yourself trying to flip bits in software or respinning your board to get things to work correctly...

-Dave

Re: LS1046A IFC Async NAND interface

Daves_Garage — Mon, 20 Nov 2023 15:47:21 GMT

I don't believe this is correct... I'm still looking for answers...

Re: LS1046A IFC Async NAND interface

stadium_aquino — Thu, 30 Nov 2023 16:13:21 GMT

This happens in multiple other places as well. E.g. SerDes lane A is RX3/TX3, lane D is RX0/TX0. The registers are numbered incorrectly too. That is, they are numbered from bit 0 to 31, but bit 0 is what you get by doing 1 << 31... This is not due to byte-swapping either, since if you e.g. read a big-endian register with a little-endian read (byte swapped) the bits (as documented) go 24 .. 31, 16 .. 23, 8..15, 0..7 (instead of 7..0, 15..8, 23..16, 31..24 like usual). I think whoever wrote the manual just loved naming the most-significant bit 0 instead of the least-significant bit.

Re: LS1046A IFC Async NAND interface

Daves_Garage — Thu, 30 Nov 2023 19:57:30 GMT

Ha... yes the ordering within registers confused me as well originally, but it became apparent that the first bit reading left to right that was labeled bit0 was actually the MSb... I adjusted my thinking while reading the reference manual after that...

But more specifically, what I was referring to was the actual bus between the IFC and the NAND part, and that the reference manual shows the bitwise reversal in picture form. There is nothing written with words that indicates the actual bus interface must be bitwise flipped. On my first spin of the board, I connected b0 from the LS1046A to b0 on the NAND chip, and b1-b1, and so on... This is exactly backwards. On the second spin of my board, I connected b0 from the LS1046A to b7 on the NAND chip, b1->b6, b2->b5, and so on, and it works correctly...

This is what I was referring to... Still an important note for others.

-Dave

Re: LS1046A IFC Async NAND interface

Daves_Garage — Mon, 29 Jul 2024 16:04:07 GMT

Well, this is officially the longest I've ever waited for a response from NXP (1.5 years to date so far)... Hoping still for a response to my original question... before the processor goes EOL anyway.