<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic LS1021A: PCIe: using multiple MSIs for one EP in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1021A-PCIe-using-multiple-MSIs-for-one-EP/m-p/546185#M1369</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I need to create a PCIe extension card which must support multiple MSIs, not MSI-X which is not possible on the card. Reading the LS1021A Reference Manual (Rev. 0, 11/2015) 10.2.47 SCFG_PEXMSIIR is the register which must be programmed as the Message Address Register to PCIe EP. The current driver pcie-designware + pci-layerscape does this.&lt;/P&gt;&lt;P&gt;So when a MSI occures the MSI Message Data contains the MSI number, e.g. 0h, 1h, 2h and so on, which is written to SCFG_PEXMSIIR in little-endian. Now reading the register definition IBS, containing the lowest byte of MSI Message Data, ignores the lowest 3 bits at all. MSI requires that MSi numbers are consequtive for one EP. How is this supposed to work if the lowest bits are ignored at all?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 07 Jul 2016 10:01:43 GMT</pubDate>
    <dc:creator>alexanderstein</dc:creator>
    <dc:date>2016-07-07T10:01:43Z</dc:date>
    <item>
      <title>LS1021A: PCIe: using multiple MSIs for one EP</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1021A-PCIe-using-multiple-MSIs-for-one-EP/m-p/546185#M1369</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I need to create a PCIe extension card which must support multiple MSIs, not MSI-X which is not possible on the card. Reading the LS1021A Reference Manual (Rev. 0, 11/2015) 10.2.47 SCFG_PEXMSIIR is the register which must be programmed as the Message Address Register to PCIe EP. The current driver pcie-designware + pci-layerscape does this.&lt;/P&gt;&lt;P&gt;So when a MSI occures the MSI Message Data contains the MSI number, e.g. 0h, 1h, 2h and so on, which is written to SCFG_PEXMSIIR in little-endian. Now reading the register definition IBS, containing the lowest byte of MSI Message Data, ignores the lowest 3 bits at all. MSI requires that MSi numbers are consequtive for one EP. How is this supposed to work if the lowest bits are ignored at all?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Jul 2016 10:01:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1021A-PCIe-using-multiple-MSIs-for-one-EP/m-p/546185#M1369</guid>
      <dc:creator>alexanderstein</dc:creator>
      <dc:date>2016-07-07T10:01:43Z</dc:date>
    </item>
  </channel>
</rss>

