topic Re: LS1026A PCIE not completing reset in Layerscape

LS1026A PCIE not completing reset

renaud — Thu, 02 Nov 2023 18:53:40 GMT

We have a ls1026A design with the RCW set as follows:

0e0d0012 10000000 00000000 00000000

33338888 40a05012 40025000 c1000000

00000000 00000000 00000000 0003dbb8

20124000 01003100 00000096 00000001

The PCIe is defined by 8888 as PCIe4x, our connection to the device is Gen2.

We do not get link as the reset sequence is not completing as shown by the PLL1RSTCTL register.

What could hold the PCIe bus like that?

renaud — Fri, 03 Nov 2023 13:06:37 GMT

Actually, the title of my request is not descriptive enough.

We have an issue with the PLL clock not locking on SD2. 100Mz clock input is there though.

renaud — Fri, 03 Nov 2023 14:32:05 GMT

Line two of RCW has been replaced by:
00008888 00e05012 40025000 c1000000

yipingwang — Tue, 07 Nov 2023 09:08:05 GMT

Investigating this problem, will update later.

renaud — Fri, 10 Nov 2023 11:21:33 GMT

We switched to use SRDS protocol 5559 and it worked with one PCIe lane. That is all we need but if you find an answer I am interested to know.

renaud — Mon, 20 Nov 2023 19:08:51 GMT

e seem to have an intermittent problem. The connected PCIE device only appears 60% of the time.