https://community.nxp.com/t5/Layerscape/LS1046-PCIe-PCIE-LINK-WIDTH-SPEED-CONTROL-register/m-p/1736401#M13454 <P>Please refer to section "1.92.43 GEN2_CTRL_OFF" in the attached&nbsp;DWC document.</P> Tue, 10 Oct 2023 08:34:46 GMT yipingwang 2023-10-10T08:34:46Z https://community.nxp.com/t5/Layerscape/LS1046-PCIe-PCIE-LINK-WIDTH-SPEED-CONTROL-register/m-p/1735580#M13445 <P>How can I get the LS1046 PCIe register description about&nbsp;PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c? I checked the LS1046 datasheet, it's no 0x80C!</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jun_li1_0-1696837049857.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/244057iE86C2E3F7615E8A2/image-size/medium?v=v2&amp;px=400" role="button" title="jun_li1_0-1696837049857.png" alt="jun_li1_0-1696837049857.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">jun_li1_0-1696837049857.png</span></span></P><P>&nbsp;</P> Mon, 09 Oct 2023 07:40:03 GMT https://community.nxp.com/t5/Layerscape/LS1046-PCIe-PCIE-LINK-WIDTH-SPEED-CONTROL-register/m-p/1735580#M13445 jun_li1 2023-10-09T07:40:03Z https://community.nxp.com/t5/Layerscape/LS1046-PCIe-PCIE-LINK-WIDTH-SPEED-CONTROL-register/m-p/1736401#M13454 <P>Please refer to section "1.92.43 GEN2_CTRL_OFF" in the attached&nbsp;DWC document.</P> Tue, 10 Oct 2023 08:34:46 GMT https://community.nxp.com/t5/Layerscape/LS1046-PCIe-PCIE-LINK-WIDTH-SPEED-CONTROL-register/m-p/1736401#M13454 yipingwang 2023-10-10T08:34:46Z