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    <title>topic Re: LS1028 RDB, Octal SPI chipselect XSPI_CS0_B XSPI_CS1_B in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1028-RDB-Octal-SPI-chipselect-XSPI-CS0-B-XSPI-CS1-B/m-p/1730546#M13399</link>
    <description>Thank you Very much Mr. Mrudang for your valuable response.&lt;BR /&gt;I will not drive these signals form CPLD as I am planning to use design without CPLD. Instead I will use pull up / pull down for the corresponding pins as per datasheet.&lt;BR /&gt;Is it ok?</description>
    <pubDate>Wed, 27 Sep 2023 13:07:52 GMT</pubDate>
    <dc:creator>mkraj</dc:creator>
    <dc:date>2023-09-27T13:07:52Z</dc:date>
    <item>
      <title>LS1028 RDB, Octal SPI chipselect XSPI_CS0_B XSPI_CS1_B</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1028-RDB-Octal-SPI-chipselect-XSPI-CS0-B-XSPI-CS1-B/m-p/1730331#M13397</link>
      <description>&lt;P&gt;Dear Expert&lt;/P&gt;&lt;P&gt;Can anyone please clarify the below points&lt;/P&gt;&lt;P&gt;1. I want to use Octal SPI chip selects&amp;nbsp;XSPI_CS0_B and&amp;nbsp; XSPI_CS1_B directly one to NOR and other to NAND. I do not want to use QSPI emulator. Is it Ok?&amp;nbsp;&lt;/P&gt;&lt;P&gt;2. What is the use of the signals&amp;nbsp;CFG_DRV,CFG_SVR0,CFG_SVR1 and&amp;nbsp;CFG_ENG_USE0 in&amp;nbsp;Flex-SPI section?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why these signals are connected to&amp;nbsp; XSPI_CS0_B, XSPI_CS1_B and&amp;nbsp;XSPI_SCK pins.&lt;/P&gt;&lt;P&gt;Thank you in advance&lt;/P&gt;&lt;P&gt;With Regards&lt;/P&gt;&lt;P&gt;Krishnam Raju M&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 27 Sep 2023 08:49:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1028-RDB-Octal-SPI-chipselect-XSPI-CS0-B-XSPI-CS1-B/m-p/1730331#M13397</guid>
      <dc:creator>mkraj</dc:creator>
      <dc:date>2023-09-27T08:49:11Z</dc:date>
    </item>
    <item>
      <title>Re: LS1028 RDB, Octal SPI chipselect XSPI_CS0_B XSPI_CS1_B</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1028-RDB-Octal-SPI-chipselect-XSPI-CS0-B-XSPI-CS1-B/m-p/1730498#M13398</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/218921"&gt;@mkraj&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;1. It is okay if you don't want to&amp;nbsp;&lt;SPAN&gt;use the QSPI emulator.&lt;BR /&gt;2. The CFG_DRV is to enable&amp;nbsp;CFG_SVR0 &amp;amp;&amp;nbsp;CFG_SVR1 signals of the design.&lt;BR /&gt;For&amp;nbsp;CFG_SVR0, please refer to section# 4.8.8.5 of the LS1028ARM.&lt;BR /&gt;For&amp;nbsp;CFG_SVR1 &amp;amp;&amp;nbsp;CFG_ENG_USE0, refer to section# 4.8.8.6 of the LS1028ARM. Also, please refer to note# 5 of Table 1 in the LS1028A datasheet which is applicable to these two signals.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Mrudang&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 27 Sep 2023 11:57:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1028-RDB-Octal-SPI-chipselect-XSPI-CS0-B-XSPI-CS1-B/m-p/1730498#M13398</guid>
      <dc:creator>mrudangshelat-13</dc:creator>
      <dc:date>2023-09-27T11:57:39Z</dc:date>
    </item>
    <item>
      <title>Re: LS1028 RDB, Octal SPI chipselect XSPI_CS0_B XSPI_CS1_B</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1028-RDB-Octal-SPI-chipselect-XSPI-CS0-B-XSPI-CS1-B/m-p/1730546#M13399</link>
      <description>Thank you Very much Mr. Mrudang for your valuable response.&lt;BR /&gt;I will not drive these signals form CPLD as I am planning to use design without CPLD. Instead I will use pull up / pull down for the corresponding pins as per datasheet.&lt;BR /&gt;Is it ok?</description>
      <pubDate>Wed, 27 Sep 2023 13:07:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1028-RDB-Octal-SPI-chipselect-XSPI-CS0-B-XSPI-CS1-B/m-p/1730546#M13399</guid>
      <dc:creator>mkraj</dc:creator>
      <dc:date>2023-09-27T13:07:52Z</dc:date>
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