LayerscapeのトピックRe: LS1046A PCIe PEX Internal registers

LS1046A PCIe PEX Internal registers

keithw — Wed, 13 Sep 2023 14:04:20 GMT

Is there any documentation for the PEX module internal configuration space registers outside of the LS1046A Reference Manual? The RTOS that I am using (VxWorks) is writing to a couple of registers that I cannot find documentation for -- PCIE_PL_PLCR (0x710) and PCIE_PL_G2CR (0x80C).

I am having trouble getting the PCIe link established on our custom board and the link appears to be breaking down after a write to the PCIE_PL_G2CR.

Re: LS1046A PCIe PEX Internal registers

Oswalag — Tue, 19 Sep 2023 18:28:38 GMT

Hello,

Is the issue present If you try with our Linux BSP ?

Re: LS1046A PCIe PEX Internal registers

keithw — Tue, 19 Sep 2023 20:09:49 GMT

I have not attempted with the Linux BSP, but the fact remains that there appear to be undocumented registers that affect the behavior of the system. I am really looking for documentation for these registers. I have managed to establish a single-lane PCIe link between our LS1046A and FPGA although I have not been successful yet on getting all four lanes working (but that is unrelated to this issue).

Re: LS1046A PCIe PEX Internal registers

Oswalag — Thu, 21 Sep 2023 20:21:51 GMT

Sorry, we do not have resources to support third-party software.
Please address your question to the Wind River technical support, they should be able to provide the description of the mentioned registers, from our side the processor's RM is the only source.

Re: LS1046A PCIe PEX Internal registers

keithw — Thu, 21 Sep 2023 20:34:53 GMT

Ok, in case anyone runs across this problem in the future, these registers are documented in other NXP processor registers. The i.MX7 manual contains definitions for these registers. It appears the same IP core is used between these two.

I'm not sure why the NXP LS1046A reference manual doesn't document all of the registers that are present.