LayerscapeのトピックLS2085A: dts entry for PHY https://community.nxp.com/t5/Layerscape/LS2085A-dts-entry-for-PHY/m-p/540546#M1324 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P>We have a custom board based on LS2085A RDB.&nbsp; In our design, we have a PHY less connection of XFI interface to FPGA as shown below.&nbsp; The dual 10G PHY are connected to emdio2.&nbsp; Can you please show an example dts definition for the below case.?&nbsp; How to show fixed link in dpl dts and mdio PHY connection in fsl dts?</P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/60402i822FB8345555963A/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /></span></P><P></P><P>Thanks</P><P>Rams</P></BODY></HTML> Fri, 17 Jun 2016 07:01:31 GMT ramasubramanian 2016-06-17T07:01:31Z LS2085A: dts entry for PHY https://community.nxp.com/t5/Layerscape/LS2085A-dts-entry-for-PHY/m-p/540546#M1324 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P>We have a custom board based on LS2085A RDB.&nbsp; In our design, we have a PHY less connection of XFI interface to FPGA as shown below.&nbsp; The dual 10G PHY are connected to emdio2.&nbsp; Can you please show an example dts definition for the below case.?&nbsp; How to show fixed link in dpl dts and mdio PHY connection in fsl dts?</P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/60402i822FB8345555963A/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /></span></P><P></P><P>Thanks</P><P>Rams</P></BODY></HTML> Fri, 17 Jun 2016 07:01:31 GMT https://community.nxp.com/t5/Layerscape/LS2085A-dts-entry-for-PHY/m-p/540546#M1324 ramasubramanian 2016-06-17T07:01:31Z