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    <title>LayerscapeのトピックRe: LS1017 ioconfig/TDR-Register</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1699348#M13013</link>
    <description>&lt;P&gt;&lt;BR /&gt;unfortunately it's not working&lt;BR /&gt;Here is my sequence:&lt;/P&gt;&lt;P&gt;LDI CPU_873, IOCONFIG;&lt;BR /&gt;IRSHIFT;&lt;BR /&gt;CPU_873: TDR:= 00080000003fc6c512ae6240000000000000000026ffd00000000000000055555555155550005000015540000005294a52aac40d0000H;&lt;BR /&gt;DRSHIFT;&lt;BR /&gt;&lt;BR /&gt;CLOCK RUNIDLE, 2000;&lt;/P&gt;&lt;P&gt;It's the same result like before&lt;/P&gt;</description>
    <pubDate>Fri, 04 Aug 2023 10:32:16 GMT</pubDate>
    <dc:creator>RS_PW</dc:creator>
    <dc:date>2023-08-04T10:32:16Z</dc:date>
    <item>
      <title>LS1017 ioconfig/TDR-Register</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1697392#M12991</link>
      <description>&lt;P&gt;&lt;BR /&gt;I'm looking for the description of the TDR-Register of the LS1017 (LS1028). I have to make an Boundary-Scan test for the Rams connected to the LS1017 (the chain and some other tests are working), I'm using Goepel. How have I to set uo the TDR-Register to make it work? I didn't find an application-note for this.&lt;BR /&gt;I found this (&lt;A href="https://community.nxp.com/t5/Layerscape/LS1027-LS1028-BoundaryScan/m-p/1598849#M11855" target="_blank"&gt;https://community.nxp.com/t5/Layerscape/LS1027-LS1028-BoundaryScan/m-p/1598849#M11855&lt;/A&gt;), but it didn't help me.&lt;BR /&gt;Thanks in advance&lt;BR /&gt;Rolf&lt;/P&gt;</description>
      <pubDate>Wed, 02 Aug 2023 08:36:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1697392#M12991</guid>
      <dc:creator>RS_PW</dc:creator>
      <dc:date>2023-08-02T08:36:07Z</dc:date>
    </item>
    <item>
      <title>Re: LS1017 ioconfig/TDR-Register</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1699324#M13012</link>
      <description>&lt;P&gt;Please refer to&amp;nbsp;&lt;A href="https://www.nxp.com/webapp/Download?colCode=AN5378" target="_blank" rel="nofollow noopener noreferrer"&gt;https://www.nxp.com/webapp/Download?colCode=AN5378&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Please try with following &lt;FONT class="&amp;amp;quothighlight&amp;quot;"&gt;&lt;STRONG&gt;TDR&lt;/STRONG&gt;&lt;/FONT&gt; value 0x00080000003fc6c512ae6240000000000000000026ffd00000000000000055555555155550005000015540000005294a52aac40d0000&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 04 Aug 2023 09:39:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1699324#M13012</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2023-08-04T09:39:04Z</dc:date>
    </item>
    <item>
      <title>Re: LS1017 ioconfig/TDR-Register</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1699348#M13013</link>
      <description>&lt;P&gt;&lt;BR /&gt;unfortunately it's not working&lt;BR /&gt;Here is my sequence:&lt;/P&gt;&lt;P&gt;LDI CPU_873, IOCONFIG;&lt;BR /&gt;IRSHIFT;&lt;BR /&gt;CPU_873: TDR:= 00080000003fc6c512ae6240000000000000000026ffd00000000000000055555555155550005000015540000005294a52aac40d0000H;&lt;BR /&gt;DRSHIFT;&lt;BR /&gt;&lt;BR /&gt;CLOCK RUNIDLE, 2000;&lt;/P&gt;&lt;P&gt;It's the same result like before&lt;/P&gt;</description>
      <pubDate>Fri, 04 Aug 2023 10:32:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1699348#M13013</guid>
      <dc:creator>RS_PW</dc:creator>
      <dc:date>2023-08-04T10:32:16Z</dc:date>
    </item>
    <item>
      <title>Re: LS1017 ioconfig/TDR-Register</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1705399#M13080</link>
      <description>&lt;P&gt;&lt;SPAN&gt;TDR is test data register and it is available in BSDL file. Opcode/instructions are also mention in BSDL file. TDR register is used to comply with IEEE1149.6 specifications and are prat of JTAG specification. Implementation of this register is SoC specific. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;1. For BSDL operation to be successful, USB power pins (USB_SVDD, USB_SDVDD and USB_HVDD) should be powered.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2. LS1028A's BSDL refers to the register "TDR_INITDATA[430]" and corresponding instructions INIT_SETUP, INIT_RUN. Customer needs to set TDR_INITDATA register with "0x000016046aa94a529400000055500001400155551555555540000000000000017fec80000000000000000048cea9146c7f8000000200" value.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;3. Once TDR_INITDATA data register is set then customer needs to feed ~2000TCLK so that BSR chain get complete. Once chain is complete than whatever is feed from TDI will be received at the TDO.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;For more information please refer AN12613.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 16 Aug 2023 05:49:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1705399#M13080</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2023-08-16T05:49:33Z</dc:date>
    </item>
    <item>
      <title>Re: LS1017 ioconfig/TDR-Register</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1705557#M13086</link>
      <description>&lt;P&gt;Thanks for the Answer,&lt;/P&gt;&lt;P&gt;I have just no boards to try it, I'll answer as soon as possible&lt;/P&gt;</description>
      <pubDate>Wed, 16 Aug 2023 08:11:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1017-ioconfig-TDR-Register/m-p/1705557#M13086</guid>
      <dc:creator>RS_PW</dc:creator>
      <dc:date>2023-08-16T08:11:03Z</dc:date>
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