LS1046A Reference clock for SerDes Lanes

Kavinravi — Wed, 26 Jul 2023 01:30:54 GMT

Hi,

We are using LS1046A in one of our projects. We would like to use 3 PCIe x 1 (Gen 2) ports to achieve 1500MBps. Since each SerDes supports a maximum of 1000MBps (10GHz), we would like to utilize both SerDes1 and SerDes2 for PCIe.

Since simultaneous selection of PCIe.1 on SerDes1 and SerDes2 is not allowed, our configuration will be:

SerDes2 for PCIe.2 x 1(Lane B) and PCIe.3 x 2(Lane C&D)

SerDes1 for PCIe.1 x 1(lane B: from DCBA in the Reference manual) [SD1_RX2_P/N SD1_TX2_P/N]

We provide 2 differential reference clocks to SD2_REF_CLK1_P/N and SD2_REF_CLK2_P/N in SerDes2.

My question is: Do we have to provide 2 differential reference clocks to SD1_REF_CLK1_P/N and SD1_REF_CLK2_P/N in SerDes1? Or, can we just give one differential reference clock to SD1_REF_CLK2_P/N as shown in LS1046A Freeway Board?

Could someone please answer my question?

Thank you for your support.

Re: LS1046A Reference clock for SerDes Lanes

Kavinravi — Wed, 26 Jul 2023 23:43:14 GMT

Answer to my question:

Every lane of SerDes2 can do PCIe Gen 1, 2, 3, i.e. each lane can generate up to 8bps. As described in Table 31-2 of the LS1046 reference manual, they can be combined to form PCIe x2 or x4 to get bandwidth of up to 16Gps (in x2 mode) or 32Gbps (in x4 mode). So, SerDes2 is more than sufficient to achieve 1500MBps and no need to utilize SerDes1 for our application.

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LS1046A Reference clock for SerDes Lanes

Re: LS1046A Reference clock for SerDes Lanes