<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Layerscape中的主题 How to debug target initialization file for DDR4  and NOR flash</title>
    <link>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1673564#M12705</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;we are working on a custom LS1043A based board with two DDR4(Part number MT40A256M16), while in LS1043ardb they used four DDR4(MT40A512M8). what sections do I need to&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;modify in CodeWarrior Target Initialization file to fit my custom board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Similarly for NOR FLASH. we used NOR flash(MT28FW02GBBA1HPC-0AAT) in our custom board and in LS1043ardb they used NOR flash(MT28EW01G).&amp;nbsp;what sections do I need to&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;modify in CodeWarrior Target Initialization file to fit my custom board.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 21 Jun 2023 10:58:38 GMT</pubDate>
    <dc:creator>dibyarekha</dc:creator>
    <dc:date>2023-06-21T10:58:38Z</dc:date>
    <item>
      <title>How to debug target initialization file for DDR4  and NOR flash</title>
      <link>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1673564#M12705</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;we are working on a custom LS1043A based board with two DDR4(Part number MT40A256M16), while in LS1043ardb they used four DDR4(MT40A512M8). what sections do I need to&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;modify in CodeWarrior Target Initialization file to fit my custom board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Similarly for NOR FLASH. we used NOR flash(MT28FW02GBBA1HPC-0AAT) in our custom board and in LS1043ardb they used NOR flash(MT28EW01G).&amp;nbsp;what sections do I need to&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;modify in CodeWarrior Target Initialization file to fit my custom board.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 21 Jun 2023 10:58:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1673564#M12705</guid>
      <dc:creator>dibyarekha</dc:creator>
      <dc:date>2023-06-21T10:58:38Z</dc:date>
    </item>
    <item>
      <title>Re: How to debug target initialization file for DDR4  and NOR flash</title>
      <link>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1674877#M12712</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/214120"&gt;@dibyarekha&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;Refer CodeWarrior Development Studio for QorIQ LS series - ARM V8 ISA section 5.5 Target Connection editor to edit target init file.&lt;BR /&gt;edit def Init_DDRC(): according to your custom board&lt;BR /&gt;&lt;BR /&gt;Adding new flash device please refer to below link.&lt;BR /&gt;Link: &lt;A href="https://www.google.com/url?sa=t&amp;amp;rct=j&amp;amp;q=&amp;amp;esrc=s&amp;amp;source=web&amp;amp;cd=&amp;amp;cad=rja&amp;amp;uact=8&amp;amp;ved=2ahUKEwj53abe3dj_AhUMVmwGHXtKAYoQFnoECA0QAQ&amp;amp;url=https%3A%2F%2Fcommunity.nxp.com%2Fpwmxy87654%2Fattachments%2Fpwmxy87654%2Fqoriq-grl%2F7636%2F2%2FAN5398%2520Adding%2520Devices%2520to%2520CW-ARMv8%2520Flash%2520Programmer.pdf&amp;amp;usg=AOvVaw1QMN6iQq0Ca7pbnnwiqVL6&amp;amp;opi=89978449" target="_blank"&gt;https://www.google.com/url?sa=t&amp;amp;rct=j&amp;amp;q=&amp;amp;esrc=s&amp;amp;source=web&amp;amp;cd=&amp;amp;cad=rja&amp;amp;uact=8&amp;amp;ved=2ahUKEwj53abe3dj_AhUMVmwGHXtKAYoQFnoECA0QAQ&amp;amp;url=https%3A%2F%2Fcommunity.nxp.com%2Fpwmxy87654%2Fattachments%2Fpwmxy87654%2Fqoriq-grl%2F7636%2F2%2FAN5398%2520Adding%2520Devices%2520to%2520CW-ARMv8%2520Flash%2520Programmer.pdf&amp;amp;usg=AOvVaw1QMN6iQq0Ca7pbnnwiqVL6&amp;amp;opi=89978449&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Mrudang&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 23 Jun 2023 09:43:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1674877#M12712</guid>
      <dc:creator>mrudangshelat-13</dc:creator>
      <dc:date>2023-06-23T09:43:31Z</dc:date>
    </item>
    <item>
      <title>Re: How to debug target initialization file for DDR4  and NOR flash</title>
      <link>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1675201#M12714</link>
      <description>Hi mrudangshelat-13&lt;BR /&gt;I already added flash device to my codewarrior IDE and I already aware how to open and edit Target init file.&lt;BR /&gt;I am asking about What are the changes Do I need to change in code to detect the Custom board DDR4 and NOR Flash.&lt;BR /&gt;DDR4 we are using DDR4 with 256 Meg x 16 and in LS1043ARDB they used DDR4 512 Meg x 8, for this what I need to change in Target init file code.&lt;BR /&gt;Similarly NOR flash used in LS1043ARDB is 1GB (MT28EW01G). We are Using NOR flash is 2GB (MT28FW02GBBA1HPC-0AAT)</description>
      <pubDate>Sat, 24 Jun 2023 04:45:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1675201#M12714</guid>
      <dc:creator>dibyarekha</dc:creator>
      <dc:date>2023-06-24T04:45:47Z</dc:date>
    </item>
    <item>
      <title>Re: How to debug target initialization file for DDR4  and NOR flash</title>
      <link>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1677880#M12744</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/214120"&gt;@dibyarekha&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;I hope you are doing well!&lt;/P&gt;
&lt;P&gt;For Custom DDR, One needs to change various parameters (number of rank/cs, data bus width, DRAM speed, timing configurations, etc) according to the datasheet of custom DDR with the help of the DDR configuration tool.&lt;/P&gt;
&lt;P&gt;Please refer to 1.1.1 Using DDR configuration tool and 1.1.1.2 Configure DDR controller in QCVS DDR Tool User Guide&lt;/P&gt;
&lt;P&gt;After that, the customer can validate DDR configuration using the Validation tool.&lt;BR /&gt;Please refer to 1.2 DDR validation in QCVS DDR Tool User Guide&lt;/P&gt;
&lt;P&gt;Once validation is done, one can generate code and make changes in TF-A accordingly.&lt;/P&gt;
&lt;P&gt;Please refer to the below-mentioned documents in LSDK.&lt;BR /&gt;TF-A DDR Driver&lt;BR /&gt;Changes in DDR initialization&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Mrudang&lt;/P&gt;</description>
      <pubDate>Wed, 28 Jun 2023 12:54:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1677880#M12744</guid>
      <dc:creator>mrudangshelat-13</dc:creator>
      <dc:date>2023-06-28T12:54:18Z</dc:date>
    </item>
    <item>
      <title>Re: How to debug target initialization file for DDR4  and NOR flash</title>
      <link>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1683631#M12795</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/203818"&gt;@mrudangshelat-13&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In&amp;nbsp;Layerscape Software Development Kit User Guide, Rev. 20.04_290520, in&amp;nbsp;Chapter 5 Bootloaders , in&amp;nbsp;5.2.4 Deploying TF-A binaries , there is&amp;nbsp;&amp;nbsp;5.2.4.1 How to compile PBL binary from RCW source file ,&amp;nbsp;5.2.4.2 How to compile U-Boot binary&amp;nbsp; and&amp;nbsp;5.2.4.4 How to compile TF-A binaries but the given commands like&amp;nbsp; i.e $ git clone &lt;A href="https://source.codeaurora.org/external/qoriq/qoriq-components/rcw" target="_blank"&gt;https://source.codeaurora.org/external/qoriq/qoriq-components/rcw&lt;/A&gt;&amp;nbsp;,&amp;nbsp;$ git clone &lt;A href="https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot.git" target="_blank"&gt;https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot.git&lt;/A&gt;&amp;nbsp;,&amp;nbsp;. $ git clone &lt;A href="https://source.codeaurora.org/external/qoriq/qoriq-components/atf" target="_blank"&gt;https://source.codeaurora.org/external/qoriq/qoriq-components/atf&amp;nbsp;&lt;/A&gt;&amp;nbsp;are not working, because they are migrated to&amp;nbsp;&lt;A href="https://www.nxp.com/design/software/embedded-software/nxp-github:NXP-GITHUB" target="_blank"&gt;GitHub&lt;/A&gt;.(&amp;nbsp;&lt;A href="https://www.nxp.com/design/software/embedded-software/nxp-github:NXP-GITHUB" target="_blank"&gt;https://www.nxp.com/design/software/embedded-software/nxp-github:NXP-GITHUB&lt;/A&gt;) on march 31 2023.&amp;nbsp;&lt;/P&gt;&lt;P&gt;My question is I want to do Boot flow with TF_A without OP-TEE. so how can I build u-boot.&lt;/P&gt;&lt;P&gt;thank you.&lt;/P&gt;</description>
      <pubDate>Fri, 07 Jul 2023 05:08:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1683631#M12795</guid>
      <dc:creator>dibyarekha</dc:creator>
      <dc:date>2023-07-07T05:08:38Z</dc:date>
    </item>
    <item>
      <title>Re: How to debug target initialization file for DDR4  and NOR flash</title>
      <link>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1683903#M12808</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/214120"&gt;@dibyarekha&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;Hope this post finds you well.&lt;BR /&gt;&lt;BR /&gt;In order to get support to your new query, please create a new ticket using the technical support web located in the following link:&lt;BR /&gt;&lt;A href="https://support.nxp.com/s/" target="_blank"&gt;https://support.nxp.com/s/&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;I would also recommend you that in order to follow this request, &lt;BR /&gt;please do not forget to mention on the case description this case number&lt;BR /&gt;which is: # 00545952&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Mrudang&lt;/P&gt;</description>
      <pubDate>Fri, 07 Jul 2023 10:31:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-to-debug-target-initialization-file-for-DDR4-and-NOR-flash/m-p/1683903#M12808</guid>
      <dc:creator>mrudangshelat-13</dc:creator>
      <dc:date>2023-07-07T10:31:17Z</dc:date>
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  </channel>
</rss>

