Layerscape中的主题 Re: UART registar (UARTMISC) specifications for LX2160A

UART registar (UARTMISC) specifications for LX2160A

shiota_kotaro — Fri, 19 May 2023 01:39:13 GMT

Hello.

Regarding the behavior of the UARTMISC register, I think there is a difference between the document description and the implementation.By setting 1, is it correct that "Interrupts occur when the interrupt mask is released"?

According to Section 29.6.1.10 of the QorIQ LX 2160 A Reference Manual, Rev. 1, 10/2021, with the following statement,it has been determined that "Interrupt Mask Settings" is 1.

The UARTIMSC register is the interrupt mask set/clear register. It is a read/write register.
On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.

When I checked the operation with the evaluation board, the reception interrupt occurs by setting 1.

Best regards.

Re: UART registar (UARTMISC) specifications for LX2160A

yipingwang — Tue, 30 May 2023 02:14:31 GMT

Can you please provide the UART register dump before and after writing to the UARTIMSC register.

Re: UART registar (UARTMISC) specifications for LX2160A

shiota_kotaro — Thu, 01 Jun 2023 05:33:53 GMT

The collected information is attached. (collected on TRACE 32)

Re: UART registar (UARTMISC) specifications for LX2160A

yipingwang — Fri, 02 Jun 2023 07:58:16 GMT

When I checked the operation with the evaluation board, the reception interrupt occurs by setting 1.
--> According to the provided register dump, when you write to the UARTIMSC register (all interrupt mask set), no bit is set in UARTRIS. This means that you are not receiving any interrupts.

Please provide the steps to reproduce this issue on LX2160ARDB.