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    <title>topic Re: LS20xxA - PCIe related question in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1649924#M12465</link>
    <description>&lt;P&gt;Hi Mrudang,&lt;BR /&gt;&lt;BR /&gt;Okay, thanks a lot for the clarification and your valuable support. It was good to have this clarified instead of assuming it to be true, which it is not.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;KHW&lt;/P&gt;</description>
    <pubDate>Mon, 15 May 2023 05:27:59 GMT</pubDate>
    <dc:creator>KHW</dc:creator>
    <dc:date>2023-05-15T05:27:59Z</dc:date>
    <item>
      <title>LS20xxA - PCIe related question</title>
      <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1643593#M12376</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Sorry if my question is silly, but can we connect more than one PCIe devices (ICs) to a single PCIe controller in general (NXP LS20xxA processor to be more specific in our case)?&lt;/P&gt;&lt;P&gt;For example, connecting four different PCIe x1 devices (ICs) to a single PCIe x4 controller of the processor.&amp;nbsp;&lt;/P&gt;&lt;P&gt;If yes, is this called PCIe bifurcation?&amp;nbsp;&lt;/P&gt;&lt;P&gt;(I think I am missing something obvious here and from previous experience/memory, it seems the above should be possible. But please also point me to the relevant section of the PCIe standard, so that I can improve my understanding of this.)&lt;/P&gt;&lt;P&gt;Any help is appreciated.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;</description>
      <pubDate>Wed, 03 May 2023 11:57:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1643593#M12376</guid>
      <dc:creator>KHW</dc:creator>
      <dc:date>2023-05-03T11:57:44Z</dc:date>
    </item>
    <item>
      <title>Re: LS20xxA - PCIe related question</title>
      <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1644543#M12392</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/213432"&gt;@KHW&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;Yes, you can connect more than one PCIe device based on the available no. of PCIe lane in the processor. For more details regarding the PCIe lane support in any layerscape processor, you can just go through the reference manual of the processor that you are thinking to to used and check in the SerDes Module chapter of the manual.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Mrudang&lt;/P&gt;</description>
      <pubDate>Thu, 04 May 2023 09:14:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1644543#M12392</guid>
      <dc:creator>mrudangshelat-13</dc:creator>
      <dc:date>2023-05-04T09:14:20Z</dc:date>
    </item>
    <item>
      <title>Re: LS20xxA - PCIe related question</title>
      <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1644608#M12394</link>
      <description>&lt;P&gt;Hi Mrudang,&lt;/P&gt;&lt;P&gt;Thanks for your answer. I did read the SerDes section of the user manual carefully, along with some other documentation and reference design, but my question was not explicitly answered anywhere.&amp;nbsp;&lt;/P&gt;&lt;P&gt;So, just to clarify again with an example related to LS2084A, as per the screenshot below, if I use the protocol setting 4B, I can use the first four lanes for four XFI ports. For &lt;EM&gt;PCIe2&amp;nbsp;&lt;/EM&gt;(2nd PCIe controller, Gen 3 here), the screenshot shows it as an x4 lane. However, I want to use it as four x1 lanes, each connected to a different device/IC. So, PCIe2 controller's four lanes will be connected to four separate x1 devices/ICs instead of single x4 device.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KHW_0-1683194424565.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/221738iDE9FBE019EBADE87/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KHW_0-1683194424565.png" alt="KHW_0-1683194424565.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Please confirm if the above will be possible.&lt;/P&gt;&lt;P&gt;And I hope it will also be applicable for other similar configurations (for example: using x2 lanes as separate x1 lane &lt;STRONG&gt;or&lt;/STRONG&gt; x8 lanes as separate x1 lanes for independent devices). I do of course understand the link (made up of at least one lane) is point to point between PCIe host/controller and device and cannot be shared with more than one device.)&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;KHW&lt;/P&gt;</description>
      <pubDate>Fri, 05 May 2023 05:29:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1644608#M12394</guid>
      <dc:creator>KHW</dc:creator>
      <dc:date>2023-05-05T05:29:55Z</dc:date>
    </item>
    <item>
      <title>Re: LS20xxA - PCIe related question</title>
      <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1647615#M12439</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/213432"&gt;@KHW&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;As per the discuss with the internal team, you can't use 4B configuration to connnect 4 x1 devices.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Mrudang&lt;/P&gt;</description>
      <pubDate>Wed, 10 May 2023 06:01:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1647615#M12439</guid>
      <dc:creator>mrudangshelat-13</dc:creator>
      <dc:date>2023-05-10T06:01:38Z</dc:date>
    </item>
    <item>
      <title>Re: LS20xxA - PCIe related question</title>
      <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1648725#M12449</link>
      <description>Thanks, Mrudang.&lt;BR /&gt;&lt;BR /&gt;Does it mean it won't work for any of the PCIe x2 or higher lane combinations as per the available configurations in the SerDes table?&lt;BR /&gt;&lt;BR /&gt;That is, if it the PCIe controller is x2/x4/x8 in the table, it has to be used that way and we can't connect multiple x1 devices to such a PCIe controller of the processor.&lt;BR /&gt;&lt;BR /&gt;Please confirm.</description>
      <pubDate>Thu, 11 May 2023 12:43:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1648725#M12449</guid>
      <dc:creator>KHW</dc:creator>
      <dc:date>2023-05-11T12:43:54Z</dc:date>
    </item>
    <item>
      <title>Re: LS20xxA - PCIe related question</title>
      <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1649148#M12457</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/213432"&gt;@KHW&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;There are x1, x2, x4 &amp;amp; x8 configuration available in SerDes 2.&lt;BR /&gt;&lt;BR /&gt;Yes, your understanding is correct. You can't connect multiple x1 devices to x2/x4/x8 PCIe controller of the processor.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Mrudang&lt;/P&gt;</description>
      <pubDate>Fri, 12 May 2023 06:46:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1649148#M12457</guid>
      <dc:creator>mrudangshelat-13</dc:creator>
      <dc:date>2023-05-12T06:46:25Z</dc:date>
    </item>
    <item>
      <title>Re: LS20xxA - PCIe related question</title>
      <link>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1649924#M12465</link>
      <description>&lt;P&gt;Hi Mrudang,&lt;BR /&gt;&lt;BR /&gt;Okay, thanks a lot for the clarification and your valuable support. It was good to have this clarified instead of assuming it to be true, which it is not.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;KHW&lt;/P&gt;</description>
      <pubDate>Mon, 15 May 2023 05:27:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS20xxA-PCIe-related-question/m-p/1649924#M12465</guid>
      <dc:creator>KHW</dc:creator>
      <dc:date>2023-05-15T05:27:59Z</dc:date>
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