PLL selection between PCI lanes

balaji_1709 — Thu, 04 May 2023 04:06:52 GMT

Hi,
I have a custom LS1046A board with the following configuration:
- VSC8514 QSGMII Phy on Serdes-1 Lane-2
- AQR113 10G Phy on Serdes-1 Lane-0
- Serdes-1 PLL-1 is clocked with 100MHz
- Serdes-1 PLL-2 is clocked with 156.25MHz

Below are the RCW configuration settings corresponding to Serdes-1:
SRDS_PRTCL_S1 - 0x1040 (XFI.9 on Lane-0 and QSGMII.6,5,10,1 on Lane-2)
SRDS_PLL_REF_CLK_SEL_S1 -0b01 (Serdes-1 PLL-1 = Lower Frequency (100MHz) and Serdes-1 PLL-2=Higher Frequency (156.25MHz))
SRDS_PLL_PD_S1 - 0b00 (Both Serdes-1 PLL-1 and Serdes-1 PLL-2 are not powered down)
SRDS_DIV_PEX_S1 - 0b01
SRDS_REFCLK_SEL_S1 - 0b0 (Separate reference clocks to both PLLs of Serdes-1)

The QSGMII MAC is not getting detected when I boot into linux.
Where should I specify the following:
- Lane-2 (on which VSC8514 is mounted) should use 100MHz from Serdes-1 PLL-1
- Lane-0 (on which AQR113 is mounted) should use 156.25MHz from Serdes-1 PLL-2

Regards
Balaji.V

Re: PLL selection between PCI lanes

yipingwang — Thu, 04 May 2023 03:47:14 GMT

This will not work. For protocol 0x1040
VSC8514 QSGMII Phy should be on Lane 2 - SerDes 1
AQR113 10G Phy should be on Lane-0 - Serdes-1

Re: PLL selection between PCI lanes

balaji_1709 — Thu, 04 May 2023 04:12:01 GMT

Thank you for your reply.

To answer my query,

2212 in the RM specifies the PLL that will be assigned to each serdes lane (PLL2 for Lane-0, PLL2 for Lane-1, PLL1 for Lane-2, PLL2 for Lane-3)

Regards

Balaji

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