LS1043 Hreset

crazy210 — Wed, 12 Apr 2023 08:34:54 GMT

LS1043 reset circuit：

The connection relationship is shown in the figure：

one PMIC，model is MC34VR500VAES.

one FPGA，model is xc7a15tcsg324.

one LS1043，model is LS1043AXE7QQB.

one power-on reset chip U3，model is ADM8611N293ACBZ-R7.

two input and gate U1, U2, model is 74LVC1G08.

one OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS U4，model is SN74LVCH244APW.

The follow is a detailed description of the circuit:

The pin 1 of U1 is connected to the power-on status output of PMIC, it indicates that the PMIC is powered on. The pin 2 of U1 are disconnected during operation.

U3 is a 200ms power-on reset, the output of U1 and the output of U3 output a reset through U2 AND gate, which is connected to pin 2 and pin 4 of U4 as inputs. Pin 18 and pin 16 of U4 are output pins, respectively are connected to FPGA, LS1043. HRRESET_B_18 and PORESET_B_18, which are all pulled up to 1.8v.

Why is HRESET_B_18 only 700Mv? See the yellow waveform below, the blue waveform is PORESET_B_18, and the waveform is 1.8V, What is the reason?

Re: LS1043 Hreset

yipingwang — Fri, 28 Apr 2023 06:22:49 GMT

Please refer to section "4.3 Power-on reset recommendations" in the attached application note.

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LS1043 Hreset

Re: LS1043 Hreset