Layerscape中的主题 How to enable DDR ECC in Uboot and Linux (LS1020A)

How to enable DDR ECC in Uboot and Linux (LS1020A)

nagireddychitta — Mon, 06 Jun 2016 11:23:19 GMT

Hi,

We are in need of enabling DDR ECC in our LS1020A based product. I have enabled ECC in DDR_SDRAM_CFG register, but when i boot the linux i see that ecc is disabled.

"[ 0.000000] Memory policy: ECC disabled, Data cache writealloc".

Can someone tell me how to enable ECC in the Linux pls?

Best Regards,

Nagi

Re: How to enable DDR ECC in Uboot and Linux (LS1020A)

Bulat — Mon, 06 Jun 2016 12:32:03 GMT

Linux uses the memory as it was defined in u-boot. Try to add into .h file following construction that is typically used with ECC:

#define CONFIG_DDR_ECC

#ifdef CONFIG_DDR_ECC

#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER

#define CONFIG_MEM_INIT_VALUE 0xdeadbeef

#endif

Regards,

Bulat

Re: How to enable DDR ECC in Uboot and Linux (LS1020A)

nagireddychitta — Tue, 07 Jun 2016 14:02:43 GMT

Hi Bulat,

Thanks for the reply.

I have enabled required bits in the memory controller related registers which are defined as macros in my uboot header file for my product. I can confirm that required registers are holding this configuration at UBoot and Linux level as well.

However, i see that linux level ecc is "on" only if we disable CONFIG_ARM_LPAE in Linux config and pass "ecc=on" as command line parameter from u-boot to linux.

This configuration forces ARMv7 not to access physical memory beyond 4GB. I am not getting any clue yet for the need of disabling CONFIG_ARM_LPAE to enable ecc in linux.

LPAE feature seems to be introduced from ARMv6 onwards, but i believe there is some strong reason why we need to disable LPAE to enable ecc in ARMv7 systems.

Pls share if you are aware of any documentation which talks about this.

Best Regards,

Nagi

Re: How to enable DDR ECC in Uboot and Linux (LS1020A)

Bulat — Wed, 08 Jun 2016 07:40:36 GMT

One linux expert told me that "Memory policy: ECC disabled, Data cache writealloc" does not relate to DDR memory at all. If you see that ECC is enabled in the DDR controller, it works in linux regardless of the mentioned report.

The report rather relates to the cache feature and refers to ARMv6. Caches of ARMv7 (both L1 and L2) support ECC, as written in the Manual "single-bit ECC correction is always enabled and is handled silently"

So basically you can simply ignore the report, treat it as an incorrect info.

Regards,

Bulat