DDR4 Configuration for LX2160A Problem

BeyongJong — Wed, 12 Apr 2023 00:24:32 GMT

We are developing the LX2160A board. However, there is a problem in setting and proceeding as follows.

DDR uses DDR4 (P/N: MT40A512M16) with On Board Memory

The code modification is as follows.
1. plat/nxp/soc-lx2160a/lx2160ardb/platform.mk CONFIG_STATIC_DDR :=1
The following three contents were tested while making changes.
NUM_OF_DDRC := 1
DDRC_NUM_DIMM := 1
DDRC_NUM_CS := 2

2. plat/nxp/soc-lx2160a/lx2160ardb/ddr_init.c
const struct ddr_cfg_regs static_1600 = {
.cs[0].bnds = 0x3ff ,
.cs[1].bnds = 0x3ff ,
.cs[0].config = 0x80050422,
.cs[1].config = 0x80000422,
.timing_cfg[3] = 0x13622100,
.timing_cfg[0] = 0xf1aa0018,
.timing_cfg[1] = 0x646a8844,
.timing_cfg[2] = 0x58023 ,
.sdram_cfg[0] = 0x65044001,
.sdram_cfg[1] = 0x401001 ,
.sdram_mode[0] = 0x6010c50 ,
.sdram_mode[1] = 0x280000 ,
.interval = 0x30c00000,
.data_init = 0xdeadbeef,
.timing_cfg[4] = 0x4502 ,
.timing_cfg[5] = 0x7401400 ,
.timing_cfg[7] = 0x3bb00000,
.zq_cntl = 0x8a090705,
.sdram_mode[1] = 0x500 ,
.sdram_mode[1] = 0x10240000,
.timing_cfg[8] = 0x9448c00 ,
.dq_map[0] = 0x32c57554,
.dq_map[1] = 0xd4bb0bd4,
.dq_map[2] = 0x2ec2f554,
.dq_map[3] = 0xd95d4001,
};

const struct dimm_params static_dimm = {
.rdimm = 0,
.primary_sdram_width = 64,
.ec_sdram_width = 8,
.n_ranks = 2,
.device_width = 16,
.mirrored_dimm = 0,
};

After setting as above, the following problem occurs.

When setting up the PHY, it is judged to be a problem in the place. Is there a way to solve this?
----------------Console Display --------------------
NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04)
0x00530003: PMU10: PHY TOTALS - NUM_DBYTES 0 NUM_NIBBLES 0 NUM_ANIBS 12
0x00560008: PMU10: CS=0x00, TSTAGES=0x031f, HDTOUT=5, 2T=0, MMISC=0 AddrMirror=0 DRAMFreq=3200MT DramType=2
0x00580008: PMU10: Pstate0 MRS MR0=0x0c50 MR1=0x0601 MR2=0x1024 MR3=0x0000 MR4=0x0000 MR5=0x0000 MR6=0x0000
ERROR: Timeout getting mail from PHY
ERROR: Wait timed out: Firmware execution on PHY 0
ERROR: Execution FW failed (error code -60)
INFO: Time before programming controller 5130 ms
PHY handshake timeout, ddr_dsr2 = 0

Re: DDR4 Configuration for LX2160A Problem

June_Lu — Fri, 14 Apr 2023 03:53:27 GMT

Please add

#define CONFIG_DDR_NODIMM

in the board .h file: “../plat/nxp/soc-lx2160/lx2160ardb/platform_def.h”

Add/fill the “struct dimm_params

ddr_raw_timing = {}” in the board ddr_init.c file

For example for LX2160ARDB , add/update the

values in the ddr_raw_timing:

struct dimm_params ddr_raw_timing = {

.n_ranks = 2,

…

};

this needs to be after the

#elif defined(CONFIG_DDR_NODIMM)

this is added in the board ddr_init.c file :

“../plat/nxp/soc-lx2160/lx2160ardb/ddr_init.c”

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DDR4 Configuration for LX2160A Problem

Re: DDR4 Configuration for LX2160A Problem