LayerscapeのトピックRe: LS1043A Secure Boot CSF header checking failure

LS1043A Secure Boot CSF header checking failure

davman — Thu, 30 Mar 2023 13:07:51 GMT

Hi,

I've been booting successfully my custom bootloader on LS1043A with secure boot enabled from QSPI memory interface.

I've located the CSF header at offset 0x17000 in OCRAM, just after the ESBC image.

If I move the CSF header further in OCRAM, @0x19000 for ex. (in order to free up some space in OCRAM), ISCB signals the error ESBC_HDR_LOC : ESCB header location not in 3.5G space.

What is this 3.5G space constraint ? What is the acceptable address range for the CSF header ?

Re: LS1043A Secure Boot CSF header checking failure

SebastianG — Mon, 03 Apr 2023 14:55:10 GMT

Hi @davman,

I hope this post finds you well,

Just to let you know that I'm still working on your questions, I will let you know as soon as I have an update. Thank you so much for your patience

Best Regards,

Sebastian

Re: LS1043A Secure Boot CSF header checking failure

SebastianG — Thu, 06 Apr 2023 18:01:52 GMT

Hello @davman ,

Could you please provide the respective logs at the time that the secure boot fails?

Best Regards,

Sebastian

Re: LS1043A Secure Boot CSF header checking failure

davman — Fri, 07 Apr 2023 06:57:04 GMT

The problem occurs during ISBC execution, not ESBC, so no logs are available. The only way ISBC has to provide an error log is by setting an error code in the SCRATCHRW2 register. In my case, this register reads 0x301, which means ERROR_ESBC_HDR_LOC.

Re: LS1043A Secure Boot CSF header checking failure

SebastianG — Fri, 07 Apr 2023 16:44:29 GMT

Hello @davman,

Could you please share with me your RCW configuration in a .bin file and a .txt file?

Best Regards,

Sebastian

Re: LS1043A Secure Boot CSF header checking failure

SebastianG — Mon, 10 Apr 2023 17:57:52 GMT

Hello @davman,

In order to solve the situation of this case we have contacted our internal team and here is the update from their side:

" The secure BootRom(i.e. ISBC) is low level BootRom that run when the system start, before all the peripherals and DDR are up and running. It is running in 32bit, and need to reserve some memory region for system use. It is kind of similar to PBI that can use only 24bit address.

Anywhere within the 3.5G range is acceptable/accessible by ISBC. You can use LSDKUG_Rev21.08, Table 22. "Unified 64 MiB memory layout of NOR/QSPI/XSPI/NAND/SD media for composite firmware on all Layerscape platforms" as a reference for "Secure boot headers". "

Meantime, could you please share with me your RCW configuration in a .bin file and a .txt file?

Best Regards,

Sebastian