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    <title>Layerscapeのトピックls1021a erratum 9942</title>
    <link>https://community.nxp.com/t5/Layerscape/ls1021a-erratum-9942/m-p/1605227#M11927</link>
    <description>&lt;P&gt;I have the U-boot source from&amp;nbsp;git://source.codeaurora.org/external/qoriq/qoriq-components/u-boot.&lt;/P&gt;&lt;P&gt;I was wondering why for the ls1021a board support (IOT, TWR, QDS, TSN), only the QDS calls&amp;nbsp;erratum_a009942_check_cpo.&lt;/P&gt;&lt;P&gt;I did notice that part of the erratum 9942 is done in the DDR driver.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;Renaud&lt;/P&gt;</description>
    <pubDate>Fri, 24 Feb 2023 12:09:05 GMT</pubDate>
    <dc:creator>renaud</dc:creator>
    <dc:date>2023-02-24T12:09:05Z</dc:date>
    <item>
      <title>ls1021a erratum 9942</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-erratum-9942/m-p/1605227#M11927</link>
      <description>&lt;P&gt;I have the U-boot source from&amp;nbsp;git://source.codeaurora.org/external/qoriq/qoriq-components/u-boot.&lt;/P&gt;&lt;P&gt;I was wondering why for the ls1021a board support (IOT, TWR, QDS, TSN), only the QDS calls&amp;nbsp;erratum_a009942_check_cpo.&lt;/P&gt;&lt;P&gt;I did notice that part of the erratum 9942 is done in the DDR driver.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;Renaud&lt;/P&gt;</description>
      <pubDate>Fri, 24 Feb 2023 12:09:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-erratum-9942/m-p/1605227#M11927</guid>
      <dc:creator>renaud</dc:creator>
      <dc:date>2023-02-24T12:09:05Z</dc:date>
    </item>
    <item>
      <title>Re: ls1021a erratum 9942</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-erratum-9942/m-p/1609172#M11980</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Thank you for contacting NXP support!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;The errata is board dependent, it's related to the DDR design on board. On ls1021aqds, it uses DDR3L UDIMM/RDIMMs, but on ls1021atwr, it uses DDR3L SDRAM discrete devices. The workaround is needed on ls1021aqds, but not needed on ls1021atwr. As for IOT/TSN board, they're not the mainstream boards included in LSDK release, I didn't use them before, I guess they don't need to apply it.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/*&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; * This additional workaround of A009942 checks the condition to determine if&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; * the CPO value set by the existing A009942 workaround needs to be updated.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; * expected optimal value, the optimal value is highly board dependent.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; */&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 03 Mar 2023 11:09:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-erratum-9942/m-p/1609172#M11980</guid>
      <dc:creator>Chavira</dc:creator>
      <dc:date>2023-03-03T11:09:42Z</dc:date>
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