https://community.nxp.com/t5/Layerscape/LS1046-CW-TAP-DDR-validation-Error/m-p/1569005#M11511 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/209457">@Hmc510</a>,</P> <P>There are few possible reasons for the error as mentioned below:</P> <OL> <LI><SPAN> The training sequence that the controller follows to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings.</SPAN><SPAN> <BR /></SPAN></LI> </OL> <OL start="2"> <LI><SPAN> Incorrect termination of MDICx signals.</SPAN></LI> </OL> <OL start="3"> <LI><SPAN> Write leveling calibration was not able to complete. This relates to improper settings of the DDR_WRLVL_CNTL register or board-level issues.</SPAN></LI> </OL> <P>&nbsp;</P> <P><SPAN>Regards,</SPAN></P> <P><SPAN>Mrudang</SPAN></P> Tue, 13 Dec 2022 13:20:20 GMT mrudangshelat-13 2022-12-13T13:20:20Z https://community.nxp.com/t5/Layerscape/LS1046-CW-TAP-DDR-validation-Error/m-p/1568975#M11510 <P>LS1046 DDR 8G . 1800MT</P><DIV class=""><DIV class=""><DIV class=""><DIV class=""><DIV class=""><DIV class=""><SPAN>I modified the code in project ATF with ddrTfa_1.c&nbsp;</SPAN></DIV><DIV class=""><SPAN>DDR validation:</SPAN></DIV></DIV></DIV></DIV></DIV></DIV><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Hmc510_0-1670931326634.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/204213i08AC081047C3943F/image-size/medium?v=v2&amp;px=400" role="button" title="Hmc510_0-1670931326634.png" alt="Hmc510_0-1670931326634.png" /></span></P><P>&nbsp;</P> Tue, 13 Dec 2022 11:59:59 GMT https://community.nxp.com/t5/Layerscape/LS1046-CW-TAP-DDR-validation-Error/m-p/1568975#M11510 Hmc510 2022-12-13T11:59:59Z https://community.nxp.com/t5/Layerscape/LS1046-CW-TAP-DDR-validation-Error/m-p/1569005#M11511 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/209457">@Hmc510</a>,</P> <P>There are few possible reasons for the error as mentioned below:</P> <OL> <LI><SPAN> The training sequence that the controller follows to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings.</SPAN><SPAN> <BR /></SPAN></LI> </OL> <OL start="2"> <LI><SPAN> Incorrect termination of MDICx signals.</SPAN></LI> </OL> <OL start="3"> <LI><SPAN> Write leveling calibration was not able to complete. This relates to improper settings of the DDR_WRLVL_CNTL register or board-level issues.</SPAN></LI> </OL> <P>&nbsp;</P> <P><SPAN>Regards,</SPAN></P> <P><SPAN>Mrudang</SPAN></P> Tue, 13 Dec 2022 13:20:20 GMT https://community.nxp.com/t5/Layerscape/LS1046-CW-TAP-DDR-validation-Error/m-p/1569005#M11511 mrudangshelat-13 2022-12-13T13:20:20Z