LayerscapeのトピックRe: LS2080A capability

LS2080A capability

JHY — Mon, 07 Mar 2016 06:49:24 GMT

Hello, experts.

LS2080A has total 16 serdes lanes for variable purpose.

So, please confirm below options are able to be implemented in LS2080A.

1. simultaneously up to 5.8G input to LS2080A and up to 2.4G output from LS2080A by PCIE.

2. vice versa 5.8G output from LS2080A and up to 2.4G input to LS2080A by PCIE

Best regards.

Re: LS2080A capability

bpe — Mon, 07 Mar 2016 08:33:38 GMT

LS2080 can support much higher than you specified data rates at the SecDes and on-chip interconnect

levels. I's ability to support a certain type of protocol or application at some data rate, however, depends on

both the application/protocol type and the implementation. Contact a distributor in your region for

advanced performance information.

Have a great day,
Platon

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Re: LS2080A capability

JHY — Tue, 08 Mar 2016 08:43:43 GMT

One more question.

It has 4 PCIE controller.

Is it possible to use 2 lanes PCIE x 4 at single serdes block like below?

Re: LS2080A capability

bpe — Wed, 09 Mar 2016 11:13:30 GMT

This is too confused. Two lanes mean PCIe x2. PCIe x4 requires four lanes. The picture displays four PCIe controllers connected

to an 8-lane SerDes, which obviously can be done in several bus width combinations. Refer to the chip Manual, Section 25.1.2.1 for available SerDes protocol combinations.

Have a great day,
Platon