LayerscapeのトピックRe: LS1046A u-boot unstable

LS1046A u-boot unstable

__OTL__ — Wed, 02 Nov 2022 04:58:29 GMT

Hi I'm bringup our own board.

U-boot is unstable and stucks in different place every time.

Here are 3 stuck log

1. stuck at DRAM INFO

U-Boot 2020.04-dirty (Nov 01 2022 - 18:09:02 +0900)

SoC: LS1046AE Rev1.0 (0x87070010)
Clock Configuration:
CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz
CPU3(A72):1600 MHz
Bus: 600 MHz DDR: 1600 MT/s FMAN: 900 MHz
Reset Configuration Word (RCW):
00000000: 0c100010 12000000 00000000 00000000
00000010: 10405577 40a00016 40000000 c1000000
00000020: 00200000 00000000 00000000 0003affc
00000030: 20004504 04201101 00000096 00000001
Model: LS1046A FRWY Board
Board: LS1046AFRWY, Rev: B, boot from QSPI
SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ
DRAM: 7.9 GiB (DDR4, 64-bit, CL=11, ECC off)

2.stuck with "Synchronous Abort" handler

U-Boot 2020.04-dirty (Nov 01 2022 - 18:09:02 +0900)

SoC: LS1046AE Rev1.0 (0x87070010)
Clock Configuration:
CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz
CPU3(A72):1600 MHz
Bus: 600 MHz DDR: 1600 MT/s FMAN: 900 MHz
Reset Configuration Word (RCW):
00000000: 0c100010 12000000 00000000 00000000
00000010: 10405577 40a00016 40000000 c1000000
00000020: 00200000 00000000 00000000 0003affc
00000030: 20004504 04201101 00000096 00000001
Model: LS1046A FRWY Board
Board: LS1046AFRWY, Rev: B, boot from QSPI
SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ
DRAM: 7.9 GiB (DDR4, 64-bit, CL=11, ECC off)
Using SERDES1 Protocol: 4160 (0x1040)
Using SERDES2 Protocol: 21879 (0x5577)
NAND: fsl_ifc_chip_init: address did not match any chip selects
0 MiB
MMC: FSL_SDHC: 0
EEPROM: Read failed.
In: serial
Out: serial
Err: serial
Net: Invalid SerDes protocol 0x1040 for LS1046AFRWY
unrecognized JEDEC id bytes: ef, 60, 18
"Synchronous Abort" handler, esr 0x96000004
elr: 000000008204a6a4 lr : 000000008204a68c (reloc)
elr: 00000000fbd786a4 lr : 00000000fbd7868c
x0 : f2a12001d2808001 x1 : 0000000000001070
x2 : 00000000fbdc8000 x3 : 0000000000001071
x4 : 00000000fbc2b880 x5 : 00000000fbc2bd60
x6 : 00000000fbdc83f0 x7 : 00000000fbdc8400
x8 : 00000000fbc43ad0 x9 : 0000000000000008
x10: 0000000000000010 x11: 00000000fbc26f8c
x12: 0000000000001238 x13: 0000000000001174
x14: 00000000fbc26fdc x15: 0000000000000002
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000fbc29dc0 x19: 00000000fbc33ad0
x20: f2a12001d2808001 x21: 0000000001a00000
x22: 0000000000000000 x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000fbc27200

Code: 90000200 91089c00 9400b6f5 17ffffd7 (f940c400)
Resetting CPU ...

resetting ...

3. stuck at the same place with case 2, but with a different synchronous handler.

Should this be considered as a DDR setting issue?

Re: LS1046A u-boot unstable

yipingwang — Wed, 02 Nov 2022 05:53:16 GMT

Probably this u-boot unstable problem is caused by the improper DDR controller configuration.

It's better to use QCVS DDRv tool to connect to your custom board to do validation and optimization to get the optimized DDR controller configuration parameters.

Re: LS1046A u-boot unstable

__OTL__ — Wed, 02 Nov 2022 07:30:08 GMT

Thanks.

I'm using QorlQ Version: 11.5.5 Build Id: 210930 to config DDR,

but for some parameters in Timing Configuration

such like tRAS=29clocks in Timing Configuration 1 and 3

once I select a different value, it get back to default value by itself.

I can't change the value...

Do you have any idea to fix the problem?

Re: LS1046A u-boot unstable

yipingwang — Thu, 03 Nov 2022 08:18:47 GMT

Please click "Advanced" on the right top of the panel, then configure "Enable timing editing" as "yes" under "SDRAM Timing Configurations".

Re: LS1046A u-boot unstable

__OTL__ — Wed, 09 Nov 2022 11:30:21 GMT

Thank you, I can edit the timing parameters now.

Sorry but now I have another problem.

I have 4x2GB DDR4 chips on the board, sharing 1 chip select.

The bus width is 64bit, no ECC.

When I use this config as attached, u-boot can only detect 1.9GB memory.

Do you know where is the problem?

Re: LS1046A u-boot unstable

yipingwang — Thu, 10 Nov 2022 08:13:06 GMT

In atf source code flexbuild_lsdk2108/components/firmware/atf, please modify "DDR Compilation Configs" in plat/nxp/soc-ls1046a/ls1046afrwy/platform.mk.