LayerscapeのトピックRe: PLL does no lock on Power-on sequence with our designed board used LS1043A

PLL does no lock on Power-on sequence with our designed board used LS1043A

yoshida08 — Thu, 22 Sep 2022 02:50:03 GMT

1. What is the PLL that causes the failure to start?
　Core/memory part only
　All PLLs

2. Factors that prevent the PLL from locking
・VDD(1.0V) power supply
・G1VDD(1.2V) power supply
・AVDD_***(1.8V/1.35V) power supply
・System clock
Are there any factors other than the above, and what is the most important factor among the above factors?
The waveform of the system clock cannot be observed at the receiving end.
In addition, IFC_Clk, IFC_WE_B, IFC_CS0_B, and IFC_OE_B signals are output even in the state where it cannot be started.

Re: PLL does no lock on Power-on sequence with our designed board used LS1043A

mrudangshelat-13 — Tue, 04 Oct 2022 12:06:26 GMT

Hi @yoshida08,

Following are some of the points to be taken care of if the PLL fails to lock:
1) Check whether the proper voltage is generated at the power pins as per the LS1043A datasheet.
2) Check whether the proper power sequence is followed as per the LS1043A datasheet.
3) Check whether the proper voltage is generated at the PLL power pins (G11, G12, G13, T19, W12 & V19) as per the LS1043A datasheet.
4) Check the clock generation & verify the selection of single-ended & Differential clocks and make sure the RCW configuration is proper.
5) The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies as per Table# 152 in the LS1043A datasheet.
6) The chip will not complete the reset sequence if SerDes reference clocks are not provided and the PLLs are enabled in the RCW (RCW SRDS_PLL_PD_S1).