<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic LS1012ARDB DDR3L Init in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1012ARDB-DDR3L-Init/m-p/1525083#M11198</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I use a different DDR3L chip(W634GU6NB):&amp;nbsp;32M  8 BANKS  16 BIT DDR3L SDRAM.&lt;/P&gt;&lt;P&gt;I use code warrior to configure the DDR3L, My DDR3L will run at 1866MT/s, but in DDR_Properties, it is 1000MT/s and I can't configure it.&lt;/P&gt;&lt;P&gt;I burned the generated DDR3L settings, bootloader stops as below, It seems that the DDR3L doesn't initialize successfully, Could you help?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;NOTICE: DDR Init Done&lt;BR /&gt;NOTICE: BL2: v2.4(release):LSDK-21.08-0-g340b20bcb&lt;BR /&gt;NOTICE: BL2: Built : 09:58:13, Sep 1 2022&lt;BR /&gt;NOTICE: BL2: Booting BL31&lt;BR /&gt;NOTICE: BL31: v2.4(release):LSDK-21.08-0-g340b20bcb&lt;BR /&gt;NOTICE: BL31: Built : 09:58:13, Sep 1 2022&lt;BR /&gt;NOTICE: Welcome to ls1012ardb BL31 Phase&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 20 Sep 2022 14:03:57 GMT</pubDate>
    <dc:creator>Hugh512</dc:creator>
    <dc:date>2022-09-20T14:03:57Z</dc:date>
    <item>
      <title>LS1012ARDB DDR3L Init</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1012ARDB-DDR3L-Init/m-p/1525083#M11198</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I use a different DDR3L chip(W634GU6NB):&amp;nbsp;32M  8 BANKS  16 BIT DDR3L SDRAM.&lt;/P&gt;&lt;P&gt;I use code warrior to configure the DDR3L, My DDR3L will run at 1866MT/s, but in DDR_Properties, it is 1000MT/s and I can't configure it.&lt;/P&gt;&lt;P&gt;I burned the generated DDR3L settings, bootloader stops as below, It seems that the DDR3L doesn't initialize successfully, Could you help?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;NOTICE: DDR Init Done&lt;BR /&gt;NOTICE: BL2: v2.4(release):LSDK-21.08-0-g340b20bcb&lt;BR /&gt;NOTICE: BL2: Built : 09:58:13, Sep 1 2022&lt;BR /&gt;NOTICE: BL2: Booting BL31&lt;BR /&gt;NOTICE: BL31: v2.4(release):LSDK-21.08-0-g340b20bcb&lt;BR /&gt;NOTICE: BL31: Built : 09:58:13, Sep 1 2022&lt;BR /&gt;NOTICE: Welcome to ls1012ardb BL31 Phase&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 20 Sep 2022 14:03:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1012ARDB-DDR3L-Init/m-p/1525083#M11198</guid>
      <dc:creator>Hugh512</dc:creator>
      <dc:date>2022-09-20T14:03:57Z</dc:date>
    </item>
    <item>
      <title>Re: LS1012ARDB DDR3L Init</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1012ARDB-DDR3L-Init/m-p/1536187#M11275</link>
      <description>&lt;P&gt;&lt;SPAN&gt;As you pointed out&amp;nbsp;&lt;/SPAN&gt;&lt;FONT class="&amp;amp;quothighlight&amp;quot;"&gt;&lt;STRONG&gt;LS1012A&lt;/STRONG&gt;&lt;/FONT&gt;&lt;SPAN&gt;&amp;nbsp;is using a different controller compared to other QorIQ devices. There is no validation selection in QCVS tool. this controller has only one chip select, 16-bit data bus, and fixed&amp;nbsp;&lt;/SPAN&gt;&lt;FONT class="&amp;amp;quothighlight&amp;quot;"&gt;&lt;STRONG&gt;1000MT/s&lt;/STRONG&gt;&lt;/FONT&gt;&lt;SPAN&gt;&amp;nbsp;data rating with DDR3L. the one chip select is very lightly loaded system with point to point connection if one x16 DRAM is used. The fixed data rate of&amp;nbsp;&lt;/SPAN&gt;&lt;FONT class="&amp;amp;quothighlight&amp;quot;"&gt;&lt;STRONG&gt;1000MT/s&lt;/STRONG&gt;&lt;/FONT&gt;&lt;SPAN&gt;&amp;nbsp;for DDR3L is relatively very slow with much margins in DRAM which are regularly are sold at 1600MT/s rating or higher. there is no clock adjust, clock is fixed at 1/2 clk delay.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 12 Oct 2022 09:52:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1012ARDB-DDR3L-Init/m-p/1536187#M11275</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2022-10-12T09:52:48Z</dc:date>
    </item>
    <item>
      <title>Re: LS1012ARDB DDR3L Init</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1012ARDB-DDR3L-Init/m-p/1567764#M11494</link>
      <description>&lt;P&gt;Dear , Thanks, finally, I success to initialize the DDR3L chip, As I assume, NXP has already did most of parameters for us, I changed little parameters&lt;/P&gt;</description>
      <pubDate>Sun, 11 Dec 2022 05:51:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1012ARDB-DDR3L-Init/m-p/1567764#M11494</guid>
      <dc:creator>Hugh512</dc:creator>
      <dc:date>2022-12-11T05:51:47Z</dc:date>
    </item>
  </channel>
</rss>

