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    <title>topic Re: LSDK on LS1046A in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1502670#M10997</link>
    <description>&lt;P&gt;I see.&amp;nbsp; This is a function of U-boot.&amp;nbsp; I've been associating this with the actual processor.&amp;nbsp; Thank you for clarifying.&amp;nbsp; I will read about U-boot.&amp;nbsp; Again, thank you and very helpful.&lt;/P&gt;</description>
    <pubDate>Mon, 08 Aug 2022 15:24:59 GMT</pubDate>
    <dc:creator>Daves_Garage</dc:creator>
    <dc:date>2022-08-08T15:24:59Z</dc:date>
    <item>
      <title>LSDK on LS1046A</title>
      <link>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1498156#M10961</link>
      <description>&lt;P&gt;Building the default configuration from LSDK 20.08 and reflashing QSPI flash on my LS1046ARDB, I see the following messages during the boot process:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;U-Boot 2021.04-dirty (Jul 28 2022 - 15:20:09 -0700)&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;SoC: LS1046AE Rev1.0 (0x87070010)&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Clock Configuration:&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;CPU0(A72):1800 MHz CPU1(A72):1800 MHz CPU2(A72):1800 MHz&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;CPU3(A72):1800 MHz&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Bus: 700 MHz DDR: 2100 MT/s FMAN: 800 MHz&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Reset Configuration Word (RCW):&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;00000000: 0e150012 10000000 00000000 00000000&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;00000010: 11335559 40005012 40025000 c1000000&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;00000020: 00000000 00000000 00000000 00238800&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;00000030: 20124000 00003101 00000096 00000001&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Model: **TRIAL HYBRID**&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Board: LS1046ARDB, boot from QSPI vBank 0&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;CPLD: V2.3&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;PCBA: V3.0&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;SERDES Reference Clocks:&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;DRAM: 15.9 GiB (DDR4, 64-bit, CL=15, ECC on)&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;DDR Chip-Select Interleaving Mode: CS0+CS1&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Using SERDES1 Protocol: 4403 (0x1133)&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Using SERDES2 Protocol: 21849 (0x5559)&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;NAND: 512 MiB&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;MMC: FSL_SDHC: 0&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Loading Environment from SPIFlash... SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;*** Warning - bad CRC, using default environment&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;EEPROM: NXID v1&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;In: serial&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Out: serial&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Err: serial&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;SEC0: RNG instantiated&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Fman1: Uploading microcode version 106.4.18&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;eth0: fm1-mac3, eth1: fm1-mac4, eth2: fm1-mac5, eth3: fm1-mac6, eth4: fm1-mac9, eth5: fm1-mac10&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="2"&gt;Hit any key to stop autoboot: 0&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;Ignoring the "Trial Hybrid" Model (I modified this string before building), I was hoping I could get an explanation&amp;nbsp; of "&lt;FONT size="2"&gt;*** Warning - bad CRC, using default environment&lt;/FONT&gt;" and why this occurs, and what the significance is.&lt;/P&gt;&lt;P&gt;Anybody knowledgeable here is welcome to enter this discussion.&amp;nbsp; I'm learning.&lt;/P&gt;&lt;P&gt;-Dave&lt;/P&gt;</description>
      <pubDate>Fri, 29 Jul 2022 16:55:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1498156#M10961</guid>
      <dc:creator>Daves_Garage</dc:creator>
      <dc:date>2022-07-29T16:55:46Z</dc:date>
    </item>
    <item>
      <title>Re: LSDK on LS1046A</title>
      <link>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1498163#M10962</link>
      <description>&lt;P&gt;U-Boot has many configuration parameters which are stored in the "Environment." There is a default environment which is compiled into U-Boot. U-Boot can also load and save its environment to permanent storage. When loading the environment, U-Boot checks the CRC to see if it is valid. If it is not valid, the default environment is used. Usually, the CRC is invalid when the environment has not yet been saved. If you have saved the environment and see this message, then something is wrong.&lt;/P&gt;</description>
      <pubDate>Fri, 29 Jul 2022 17:12:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1498163#M10962</guid>
      <dc:creator>stadium_aquino</dc:creator>
      <dc:date>2022-07-29T17:12:29Z</dc:date>
    </item>
    <item>
      <title>Re: LSDK on LS1046A</title>
      <link>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1502636#M10993</link>
      <description>&lt;P&gt;Presumably there are details on this "environment", and what goes into generating it?&amp;nbsp; Can you possible point me in the right direction to a document or website?&amp;nbsp; I am currently investigating.&lt;/P&gt;&lt;P&gt;Thank you for your response.&lt;/P&gt;</description>
      <pubDate>Mon, 08 Aug 2022 14:19:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1502636#M10993</guid>
      <dc:creator>Daves_Garage</dc:creator>
      <dc:date>2022-08-08T14:19:35Z</dc:date>
    </item>
    <item>
      <title>Re: LSDK on LS1046A</title>
      <link>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1502665#M10996</link>
      <description>&lt;P&gt;&lt;A href="https://u-boot.readthedocs.io/en/latest/usage/environment.html" target="_blank"&gt;https://u-boot.readthedocs.io/en/latest/usage/environment.html&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Aug 2022 15:19:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1502665#M10996</guid>
      <dc:creator>stadium_aquino</dc:creator>
      <dc:date>2022-08-08T15:19:12Z</dc:date>
    </item>
    <item>
      <title>Re: LSDK on LS1046A</title>
      <link>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1502670#M10997</link>
      <description>&lt;P&gt;I see.&amp;nbsp; This is a function of U-boot.&amp;nbsp; I've been associating this with the actual processor.&amp;nbsp; Thank you for clarifying.&amp;nbsp; I will read about U-boot.&amp;nbsp; Again, thank you and very helpful.&lt;/P&gt;</description>
      <pubDate>Mon, 08 Aug 2022 15:24:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LSDK-on-LS1046A/m-p/1502670#M10997</guid>
      <dc:creator>Daves_Garage</dc:creator>
      <dc:date>2022-08-08T15:24:59Z</dc:date>
    </item>
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