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    <title>LayerscapeのトピックRe: ls1021a with DDR4</title>
    <link>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1484119#M10818</link>
    <description>&lt;P&gt;Hi,&lt;BR /&gt;&lt;BR /&gt;We are also facing similar issue with ls1021a custom board. We are trying to initialize DDR4 memory device. But u-boot hangs at following function&lt;BR /&gt;gd-&amp;gt;ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);&lt;BR /&gt;&lt;BR /&gt;Let me know if you were able to initialize ddr4 memory successfully.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 04 Jul 2022 14:37:19 GMT</pubDate>
    <dc:creator>Anonymous</dc:creator>
    <dc:date>2022-07-04T14:37:19Z</dc:date>
    <item>
      <title>ls1021a with DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1344522#M8953</link>
      <description>&lt;P&gt;Dear sirs,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could you provide DDR4 configuration example for ls1021a?&lt;/P&gt;&lt;P&gt;We have a customized board with DDR4 but we failed to boot.&lt;/P&gt;&lt;P&gt;Thanks for your help&lt;/P&gt;</description>
      <pubDate>Thu, 23 Sep 2021 02:04:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1344522#M8953</guid>
      <dc:creator>kuanlun_chiu</dc:creator>
      <dc:date>2021-09-23T02:04:40Z</dc:date>
    </item>
    <item>
      <title>Re: ls1021a with DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1344599#M8957</link>
      <description>&lt;P&gt;We do not have LS1021A developement&amp;nbsp; boards with DDR4, as a result we do not have initialization examples for such cases.&lt;/P&gt;
&lt;P&gt;You can use initialization files for the LS1043A (e.g.LS1043ARDB board), these devices have the same DDR controller, so all parameters are the same.&lt;/P&gt;
&lt;P&gt;The difference is in CSn_BNDS setting, for the LS1021A you need to use absolute addresses (like in DDR3L case). DDR address space starts at 0x80000000.&lt;/P&gt;
&lt;P&gt;Values of DDR_WRLVL_CNTL_n and DDR_SDRAM_CLK_CNTL are board dependent, we typically recommend to use DDRv tool to define optimal values.&lt;/P&gt;
&lt;P&gt;Another important point is settings of DQ_MAP registers in case of DDR4, these should reflect actual bit mapping between DDR controller and DDR4 SDRAMs. Otherwise the DDR controller can not start up.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Bulat&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 23 Sep 2021 04:10:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1344599#M8957</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2021-09-23T04:10:50Z</dc:date>
    </item>
    <item>
      <title>Re: ls1021a with DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1484119#M10818</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;&lt;BR /&gt;We are also facing similar issue with ls1021a custom board. We are trying to initialize DDR4 memory device. But u-boot hangs at following function&lt;BR /&gt;gd-&amp;gt;ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);&lt;BR /&gt;&lt;BR /&gt;Let me know if you were able to initialize ddr4 memory successfully.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 04 Jul 2022 14:37:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1484119#M10818</guid>
      <dc:creator>Anonymous</dc:creator>
      <dc:date>2022-07-04T14:37:19Z</dc:date>
    </item>
    <item>
      <title>Re: ls1021a with DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1551964#M11391</link>
      <description>&lt;P class=""&gt;&lt;SPAN class=""&gt;hello &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;When I use DDR4 for ls1021atwr , should the DDR_SDRAM_CFG register(default vlues is 0x07000000h) value be set to 0x05000000h? and &lt;SPAN&gt;and if there are any other necessary Settings&lt;/SPAN&gt;?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;thanks!&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 10 Nov 2022 12:08:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-with-DDR4/m-p/1551964#M11391</guid>
      <dc:creator>ZzlYanG_cn</dc:creator>
      <dc:date>2022-11-10T12:08:20Z</dc:date>
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