<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic RGMII tx error in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/RGMII-tx-error/m-p/1484110#M10817</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I've a problem with my custom board with a LS1020A CPU.&lt;/P&gt;&lt;P&gt;I've a RGMII PHY (Marvell 88e1510-a0) connected to eTSEC3 like the LS1021A board.&lt;/P&gt;&lt;P&gt;The PHY is detected by U-Boot through MDIO on the good eTSEC port:&lt;/P&gt;&lt;LI-SPOILER&gt;=&amp;gt; mdio list&lt;BR /&gt;ethernet@2d10000:&lt;BR /&gt;ethernet@2d50000:&lt;BR /&gt;ethernet@2d90000:&lt;BR /&gt;1 - Marvell 88E151x &amp;lt;--&amp;gt; ethernet@2d90000&lt;/LI-SPOILER&gt;&lt;P&gt;The link with my switch is up and the PHY model is correct (PHY 0x01):&lt;/P&gt;&lt;LI-SPOILER&gt;=&amp;gt; mii info&lt;BR /&gt;PHY 0x01: OUI = 0x5043, Model = 0x1D, Rev = 0x01, 1000baseT, FDX&lt;BR /&gt;PHY 0x1F: OUI = 0x0000, Model = 0x00, Rev = 0x00, 1000baseX, HDX&lt;BR /&gt;&lt;BR /&gt;&lt;P&gt;=&amp;gt; mii dump 1 0&lt;BR /&gt;0. (1000) -- PHY control register --&lt;BR /&gt;(8000:0000) 0.15 = 0 reset&lt;BR /&gt;(4000:0000) 0.14 = 0 loopback&lt;BR /&gt;(2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps&lt;BR /&gt;(1000:1000) 0.12 = 1 A/N enable&lt;BR /&gt;(0800:0000) 0.11 = 0 power-down&lt;BR /&gt;(0400:0000) 0.10 = 0 isolate&lt;BR /&gt;(0200:0000) 0. 9 = 0 restart A/N&lt;BR /&gt;(0100:0000) 0. 8 = 0 duplex = half&lt;BR /&gt;(0080:0000) 0. 7 = 0 collision test enable&lt;BR /&gt;(003f:0000) 0. 5- 0 = 0 (reserved)&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 1&lt;BR /&gt;1. (796d) -- PHY status register --&lt;BR /&gt;(8000:0000) 1.15 = 0 100BASE-T4 able&lt;BR /&gt;(4000:4000) 1.14 = 1 100BASE-X full duplex able&lt;BR /&gt;(2000:2000) 1.13 = 1 100BASE-X half duplex able&lt;BR /&gt;(1000:1000) 1.12 = 1 10 Mbps full duplex able&lt;BR /&gt;(0800:0800) 1.11 = 1 10 Mbps half duplex able&lt;BR /&gt;(0400:0000) 1.10 = 0 100BASE-T2 full duplex able&lt;BR /&gt;(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able&lt;BR /&gt;(0100:0100) 1. 8 = 1 extended status&lt;BR /&gt;(0080:0000) 1. 7 = 0 (reserved)&lt;BR /&gt;(0040:0040) 1. 6 = 1 MF preamble suppression&lt;BR /&gt;(0020:0020) 1. 5 = 1 A/N complete&lt;BR /&gt;(0010:0000) 1. 4 = 0 remote fault&lt;BR /&gt;(0008:0008) 1. 3 = 1 A/N able&lt;BR /&gt;(0004:0004) 1. 2 = 1 link status&lt;BR /&gt;(0002:0000) 1. 1 = 0 jabber detect&lt;BR /&gt;(0001:0001) 1. 0 = 1 extended capabilities&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 2&lt;BR /&gt;2. (0141) -- PHY ID 1 register --&lt;BR /&gt;(ffff:0141) 2.15- 0 = 321 OUI portion&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 3&lt;BR /&gt;3. (0dd1) -- PHY ID 2 register --&lt;BR /&gt;(fc00:0c00) 3.15-10 = 3 OUI portion&lt;BR /&gt;(03f0:01d0) 3. 9- 4 = 29 manufacturer part number&lt;BR /&gt;(000f:0001) 3. 3- 0 = 1 manufacturer rev. number&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 4&lt;BR /&gt;4. (01e1) -- Autonegotiation advertisement register --&lt;BR /&gt;(8000:0000) 4.15 = 0 next page able&lt;BR /&gt;(4000:0000) 4.14 = 0 (reserved)&lt;BR /&gt;(2000:0000) 4.13 = 0 remote fault&lt;BR /&gt;(1000:0000) 4.12 = 0 (reserved)&lt;BR /&gt;(0800:0000) 4.11 = 0 asymmetric pause&lt;BR /&gt;(0400:0000) 4.10 = 0 pause enable&lt;BR /&gt;(0200:0000) 4. 9 = 0 100BASE-T4 able&lt;BR /&gt;(0100:0100) 4. 8 = 1 100BASE-TX full duplex able&lt;BR /&gt;(0080:0080) 4. 7 = 1 100BASE-TX able&lt;BR /&gt;(0040:0040) 4. 6 = 1 10BASE-T full duplex able&lt;BR /&gt;(0020:0020) 4. 5 = 1 10BASE-T able&lt;BR /&gt;(001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3 CSMA/CD&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 5&lt;BR /&gt;5. (c5e1) -- Autonegotiation partner abilities register --&lt;BR /&gt;(8000:8000) 5.15 = 1 next page able&lt;BR /&gt;(4000:4000) 5.14 = 1 acknowledge&lt;BR /&gt;(2000:0000) 5.13 = 0 remote fault&lt;BR /&gt;(1000:0000) 5.12 = 0 (reserved)&lt;BR /&gt;(0800:0000) 5.11 = 0 asymmetric pause able&lt;BR /&gt;(0400:0400) 5.10 = 1 pause able&lt;BR /&gt;(0200:0000) 5. 9 = 0 100BASE-T4 able&lt;BR /&gt;(0100:0100) 5. 8 = 1 100BASE-X full duplex able&lt;BR /&gt;(0080:0080) 5. 7 = 1 100BASE-TX able&lt;BR /&gt;(0040:0040) 5. 6 = 1 10BASE-T full duplex able&lt;BR /&gt;(0020:0020) 5. 5 = 1 10BASE-T able&lt;BR /&gt;(001f:0001) 5. 4- 0 = 1 partner selector = IEEE 802.3 CSMA/CD&lt;/P&gt;&lt;/LI-SPOILER&gt;&lt;P&gt;At boot, driver is probed and recognized as prime:&lt;/P&gt;&lt;LI-SPOILER&gt;mdio_register: non unique device name 'ethernet@2d50000'&lt;BR /&gt;, eth-1: ethernet@2d50000, eth0: ethernet@2d90000 [PRIME]&lt;/LI-SPOILER&gt;&lt;P&gt;When I try to make a dchp command I have a timeout error. Same thing for the ping command if I set an IP:&lt;/P&gt;&lt;LI-SPOILER&gt;&lt;P&gt;=&amp;gt; dhcp&lt;BR /&gt;tsec_probe: Name: ethernet@2d10000&lt;BR /&gt;mdio_register: non unique device name 'ethernet@2d10000'&lt;BR /&gt;tsec_probe: Name: ethernet@2d50000&lt;BR /&gt;mdio_register: non unique device name 'ethernet@2d50000'&lt;BR /&gt;tsec_init: Name: ethernet@2d90000&lt;BR /&gt;ethernet@2d90000: tsec: halt&lt;BR /&gt;ethernet@2d90000: TSEC Ethernet [02d90000]&lt;BR /&gt;Speed: 1000, full duplex&lt;BR /&gt;Link: up&lt;BR /&gt;BOOTP broadcast 1&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers not full&lt;BR /&gt;ethernet@2d90000: tsec: tx_idx: 0&lt;BR /&gt;ethernet@2d90000: tsec: status: 0x0&lt;BR /&gt;ethernet@2d90000: tsec: length: 342&lt;BR /&gt;ethernet@2d90000: tsec: buffer: 0x9ffed540&lt;BR /&gt;ethernet@2d90000: tsec: &amp;amp;priv-&amp;gt;txbd[priv-&amp;gt;tx_idx]: 0x9ef2db40&lt;BR /&gt;ethernet@2d90000: tsec: status: 0x0&lt;BR /&gt;ethernet@2d90000: tsec: tx error. Status: 0x9c00&lt;BR /&gt;BOOTP broadcast 2&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;BOOTP broadcast 3&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;BOOTP broadcast 4&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;BOOTP broadcast 5&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;ethernet@2d90000: tsec: halt&lt;/P&gt;&lt;P&gt;Abort&lt;BR /&gt;=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;/P&gt;&lt;/LI-SPOILER&gt;&lt;P&gt;I added some log to have more information. Main error is "&lt;EM&gt;ethernet@2d90000: tsec: tx error. Status: 0x9c00&lt;/EM&gt;". The txbd status is always TXBD_READY.&lt;/P&gt;&lt;P&gt;The device tree is:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;...
 
&amp;amp;enet0 {
         phy-handle = &amp;lt;&amp;amp;rgmii_phy2&amp;gt;;
         phy-connection-type = "rgmii-id";
         status = "okay";
 };
 
 &amp;amp;enet1 {
         tbi-handle = &amp;lt;&amp;amp;tbi1&amp;gt;;
         phy-handle = &amp;lt;&amp;amp;sgmii_phy0&amp;gt;;
         phy-connection-type = "sgmii";
         status = "okay";

 };
 
 &amp;amp;enet2 {
         phy-handle = &amp;lt;&amp;amp;rgmii_phy1&amp;gt;;
         phy-connection-type = "rgmii-id";
         status = "okay";
 };

...

&amp;amp;mdio0 {
         sgmii_phy0: ethernet-phy@0 { /* DSP/Serdes MDIO Address is unallocated (Not Implemented) */
                 reg = &amp;lt;0x0&amp;gt;;
         };
 
         rgmii_phy1: ethernet-phy@1 { /* PHY MDIO Address is 1 */
                 compatible = "marvell,88E1510";
                 device_type = "ethernet-phy";
                 interrupt-parent = &amp;lt;&amp;amp;gic&amp;gt;;
                 interrupts = &amp;lt;GIC_SPI 167 IRQ_TYPE_EDGE_RISING&amp;gt;; // lore.kernel.org/lkml/20191109105642.30700-1-olteanv@gmail.com
                 reg = &amp;lt;0x1&amp;gt;;
         };
 
         rgmii_phy2: ethernet-phy@2 { /* SWITCH MDIO Address is 2 (Not Used in U-Boot) */
                 reg = &amp;lt;0x2&amp;gt;;
         };
 
         /* SGMII PCS for enet0 - Not Used in U-Boot */
         tbi0: tbi-phy@1f {
                 reg = &amp;lt;0x1f&amp;gt;;
                 device_type = "tbi-phy";
         };
 };
 
 &amp;amp;mdio1 {
         /* SGMII PCS for enet1 - Not Used in U-Boot */
         tbi1: tbi-phy@1f {
                 reg = &amp;lt;0x1f&amp;gt;;
                 device_type = "tbi-phy";
         };
 };

...&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your help&lt;/P&gt;</description>
    <pubDate>Mon, 04 Jul 2022 14:19:25 GMT</pubDate>
    <dc:creator>jb2</dc:creator>
    <dc:date>2022-07-04T14:19:25Z</dc:date>
    <item>
      <title>RGMII tx error</title>
      <link>https://community.nxp.com/t5/Layerscape/RGMII-tx-error/m-p/1484110#M10817</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I've a problem with my custom board with a LS1020A CPU.&lt;/P&gt;&lt;P&gt;I've a RGMII PHY (Marvell 88e1510-a0) connected to eTSEC3 like the LS1021A board.&lt;/P&gt;&lt;P&gt;The PHY is detected by U-Boot through MDIO on the good eTSEC port:&lt;/P&gt;&lt;LI-SPOILER&gt;=&amp;gt; mdio list&lt;BR /&gt;ethernet@2d10000:&lt;BR /&gt;ethernet@2d50000:&lt;BR /&gt;ethernet@2d90000:&lt;BR /&gt;1 - Marvell 88E151x &amp;lt;--&amp;gt; ethernet@2d90000&lt;/LI-SPOILER&gt;&lt;P&gt;The link with my switch is up and the PHY model is correct (PHY 0x01):&lt;/P&gt;&lt;LI-SPOILER&gt;=&amp;gt; mii info&lt;BR /&gt;PHY 0x01: OUI = 0x5043, Model = 0x1D, Rev = 0x01, 1000baseT, FDX&lt;BR /&gt;PHY 0x1F: OUI = 0x0000, Model = 0x00, Rev = 0x00, 1000baseX, HDX&lt;BR /&gt;&lt;BR /&gt;&lt;P&gt;=&amp;gt; mii dump 1 0&lt;BR /&gt;0. (1000) -- PHY control register --&lt;BR /&gt;(8000:0000) 0.15 = 0 reset&lt;BR /&gt;(4000:0000) 0.14 = 0 loopback&lt;BR /&gt;(2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps&lt;BR /&gt;(1000:1000) 0.12 = 1 A/N enable&lt;BR /&gt;(0800:0000) 0.11 = 0 power-down&lt;BR /&gt;(0400:0000) 0.10 = 0 isolate&lt;BR /&gt;(0200:0000) 0. 9 = 0 restart A/N&lt;BR /&gt;(0100:0000) 0. 8 = 0 duplex = half&lt;BR /&gt;(0080:0000) 0. 7 = 0 collision test enable&lt;BR /&gt;(003f:0000) 0. 5- 0 = 0 (reserved)&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 1&lt;BR /&gt;1. (796d) -- PHY status register --&lt;BR /&gt;(8000:0000) 1.15 = 0 100BASE-T4 able&lt;BR /&gt;(4000:4000) 1.14 = 1 100BASE-X full duplex able&lt;BR /&gt;(2000:2000) 1.13 = 1 100BASE-X half duplex able&lt;BR /&gt;(1000:1000) 1.12 = 1 10 Mbps full duplex able&lt;BR /&gt;(0800:0800) 1.11 = 1 10 Mbps half duplex able&lt;BR /&gt;(0400:0000) 1.10 = 0 100BASE-T2 full duplex able&lt;BR /&gt;(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able&lt;BR /&gt;(0100:0100) 1. 8 = 1 extended status&lt;BR /&gt;(0080:0000) 1. 7 = 0 (reserved)&lt;BR /&gt;(0040:0040) 1. 6 = 1 MF preamble suppression&lt;BR /&gt;(0020:0020) 1. 5 = 1 A/N complete&lt;BR /&gt;(0010:0000) 1. 4 = 0 remote fault&lt;BR /&gt;(0008:0008) 1. 3 = 1 A/N able&lt;BR /&gt;(0004:0004) 1. 2 = 1 link status&lt;BR /&gt;(0002:0000) 1. 1 = 0 jabber detect&lt;BR /&gt;(0001:0001) 1. 0 = 1 extended capabilities&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 2&lt;BR /&gt;2. (0141) -- PHY ID 1 register --&lt;BR /&gt;(ffff:0141) 2.15- 0 = 321 OUI portion&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 3&lt;BR /&gt;3. (0dd1) -- PHY ID 2 register --&lt;BR /&gt;(fc00:0c00) 3.15-10 = 3 OUI portion&lt;BR /&gt;(03f0:01d0) 3. 9- 4 = 29 manufacturer part number&lt;BR /&gt;(000f:0001) 3. 3- 0 = 1 manufacturer rev. number&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 4&lt;BR /&gt;4. (01e1) -- Autonegotiation advertisement register --&lt;BR /&gt;(8000:0000) 4.15 = 0 next page able&lt;BR /&gt;(4000:0000) 4.14 = 0 (reserved)&lt;BR /&gt;(2000:0000) 4.13 = 0 remote fault&lt;BR /&gt;(1000:0000) 4.12 = 0 (reserved)&lt;BR /&gt;(0800:0000) 4.11 = 0 asymmetric pause&lt;BR /&gt;(0400:0000) 4.10 = 0 pause enable&lt;BR /&gt;(0200:0000) 4. 9 = 0 100BASE-T4 able&lt;BR /&gt;(0100:0100) 4. 8 = 1 100BASE-TX full duplex able&lt;BR /&gt;(0080:0080) 4. 7 = 1 100BASE-TX able&lt;BR /&gt;(0040:0040) 4. 6 = 1 10BASE-T full duplex able&lt;BR /&gt;(0020:0020) 4. 5 = 1 10BASE-T able&lt;BR /&gt;(001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3 CSMA/CD&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;=&amp;gt; mii dump 1 5&lt;BR /&gt;5. (c5e1) -- Autonegotiation partner abilities register --&lt;BR /&gt;(8000:8000) 5.15 = 1 next page able&lt;BR /&gt;(4000:4000) 5.14 = 1 acknowledge&lt;BR /&gt;(2000:0000) 5.13 = 0 remote fault&lt;BR /&gt;(1000:0000) 5.12 = 0 (reserved)&lt;BR /&gt;(0800:0000) 5.11 = 0 asymmetric pause able&lt;BR /&gt;(0400:0400) 5.10 = 1 pause able&lt;BR /&gt;(0200:0000) 5. 9 = 0 100BASE-T4 able&lt;BR /&gt;(0100:0100) 5. 8 = 1 100BASE-X full duplex able&lt;BR /&gt;(0080:0080) 5. 7 = 1 100BASE-TX able&lt;BR /&gt;(0040:0040) 5. 6 = 1 10BASE-T full duplex able&lt;BR /&gt;(0020:0020) 5. 5 = 1 10BASE-T able&lt;BR /&gt;(001f:0001) 5. 4- 0 = 1 partner selector = IEEE 802.3 CSMA/CD&lt;/P&gt;&lt;/LI-SPOILER&gt;&lt;P&gt;At boot, driver is probed and recognized as prime:&lt;/P&gt;&lt;LI-SPOILER&gt;mdio_register: non unique device name 'ethernet@2d50000'&lt;BR /&gt;, eth-1: ethernet@2d50000, eth0: ethernet@2d90000 [PRIME]&lt;/LI-SPOILER&gt;&lt;P&gt;When I try to make a dchp command I have a timeout error. Same thing for the ping command if I set an IP:&lt;/P&gt;&lt;LI-SPOILER&gt;&lt;P&gt;=&amp;gt; dhcp&lt;BR /&gt;tsec_probe: Name: ethernet@2d10000&lt;BR /&gt;mdio_register: non unique device name 'ethernet@2d10000'&lt;BR /&gt;tsec_probe: Name: ethernet@2d50000&lt;BR /&gt;mdio_register: non unique device name 'ethernet@2d50000'&lt;BR /&gt;tsec_init: Name: ethernet@2d90000&lt;BR /&gt;ethernet@2d90000: tsec: halt&lt;BR /&gt;ethernet@2d90000: TSEC Ethernet [02d90000]&lt;BR /&gt;Speed: 1000, full duplex&lt;BR /&gt;Link: up&lt;BR /&gt;BOOTP broadcast 1&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers not full&lt;BR /&gt;ethernet@2d90000: tsec: tx_idx: 0&lt;BR /&gt;ethernet@2d90000: tsec: status: 0x0&lt;BR /&gt;ethernet@2d90000: tsec: length: 342&lt;BR /&gt;ethernet@2d90000: tsec: buffer: 0x9ffed540&lt;BR /&gt;ethernet@2d90000: tsec: &amp;amp;priv-&amp;gt;txbd[priv-&amp;gt;tx_idx]: 0x9ef2db40&lt;BR /&gt;ethernet@2d90000: tsec: status: 0x0&lt;BR /&gt;ethernet@2d90000: tsec: tx error. Status: 0x9c00&lt;BR /&gt;BOOTP broadcast 2&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;BOOTP broadcast 3&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;BOOTP broadcast 4&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;BOOTP broadcast 5&lt;BR /&gt;tsec_send: Len: 342&lt;BR /&gt;ethernet@2d90000: tsec: tx buffers full&lt;BR /&gt;ethernet@2d90000: tsec: halt&lt;/P&gt;&lt;P&gt;Abort&lt;BR /&gt;=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;/P&gt;&lt;/LI-SPOILER&gt;&lt;P&gt;I added some log to have more information. Main error is "&lt;EM&gt;ethernet@2d90000: tsec: tx error. Status: 0x9c00&lt;/EM&gt;". The txbd status is always TXBD_READY.&lt;/P&gt;&lt;P&gt;The device tree is:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;...
 
&amp;amp;enet0 {
         phy-handle = &amp;lt;&amp;amp;rgmii_phy2&amp;gt;;
         phy-connection-type = "rgmii-id";
         status = "okay";
 };
 
 &amp;amp;enet1 {
         tbi-handle = &amp;lt;&amp;amp;tbi1&amp;gt;;
         phy-handle = &amp;lt;&amp;amp;sgmii_phy0&amp;gt;;
         phy-connection-type = "sgmii";
         status = "okay";

 };
 
 &amp;amp;enet2 {
         phy-handle = &amp;lt;&amp;amp;rgmii_phy1&amp;gt;;
         phy-connection-type = "rgmii-id";
         status = "okay";
 };

...

&amp;amp;mdio0 {
         sgmii_phy0: ethernet-phy@0 { /* DSP/Serdes MDIO Address is unallocated (Not Implemented) */
                 reg = &amp;lt;0x0&amp;gt;;
         };
 
         rgmii_phy1: ethernet-phy@1 { /* PHY MDIO Address is 1 */
                 compatible = "marvell,88E1510";
                 device_type = "ethernet-phy";
                 interrupt-parent = &amp;lt;&amp;amp;gic&amp;gt;;
                 interrupts = &amp;lt;GIC_SPI 167 IRQ_TYPE_EDGE_RISING&amp;gt;; // lore.kernel.org/lkml/20191109105642.30700-1-olteanv@gmail.com
                 reg = &amp;lt;0x1&amp;gt;;
         };
 
         rgmii_phy2: ethernet-phy@2 { /* SWITCH MDIO Address is 2 (Not Used in U-Boot) */
                 reg = &amp;lt;0x2&amp;gt;;
         };
 
         /* SGMII PCS for enet0 - Not Used in U-Boot */
         tbi0: tbi-phy@1f {
                 reg = &amp;lt;0x1f&amp;gt;;
                 device_type = "tbi-phy";
         };
 };
 
 &amp;amp;mdio1 {
         /* SGMII PCS for enet1 - Not Used in U-Boot */
         tbi1: tbi-phy@1f {
                 reg = &amp;lt;0x1f&amp;gt;;
                 device_type = "tbi-phy";
         };
 };

...&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your help&lt;/P&gt;</description>
      <pubDate>Mon, 04 Jul 2022 14:19:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/RGMII-tx-error/m-p/1484110#M10817</guid>
      <dc:creator>jb2</dc:creator>
      <dc:date>2022-07-04T14:19:25Z</dc:date>
    </item>
    <item>
      <title>Re: RGMII tx error</title>
      <link>https://community.nxp.com/t5/Layerscape/RGMII-tx-error/m-p/1486248#M10845</link>
      <description>&lt;P&gt;We found the problem, RCW was not good.&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jul 2022 13:42:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/RGMII-tx-error/m-p/1486248#M10845</guid>
      <dc:creator>jb2</dc:creator>
      <dc:date>2022-07-07T13:42:37Z</dc:date>
    </item>
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