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    <title>LayerscapeのトピックSMBCLK AND SMBDATA OF PCIE</title>
    <link>https://community.nxp.com/t5/Layerscape/SMBCLK-AND-SMBDATA-OF-PCIE/m-p/1470434#M10646</link>
    <description>&lt;P&gt;I am designing a new hardware using LS1046 and PCIe. Is it mandatory to connect SMBCLK and SMB DATA of PCIE to I2C bus of CPU? I am confused why it is connected to I2C in the reference designs.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 08 Jun 2022 07:32:24 GMT</pubDate>
    <dc:creator>Ellu24</dc:creator>
    <dc:date>2022-06-08T07:32:24Z</dc:date>
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      <title>SMBCLK AND SMBDATA OF PCIE</title>
      <link>https://community.nxp.com/t5/Layerscape/SMBCLK-AND-SMBDATA-OF-PCIE/m-p/1470434#M10646</link>
      <description>&lt;P&gt;I am designing a new hardware using LS1046 and PCIe. Is it mandatory to connect SMBCLK and SMB DATA of PCIE to I2C bus of CPU? I am confused why it is connected to I2C in the reference designs.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 08 Jun 2022 07:32:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/SMBCLK-AND-SMBDATA-OF-PCIE/m-p/1470434#M10646</guid>
      <dc:creator>Ellu24</dc:creator>
      <dc:date>2022-06-08T07:32:24Z</dc:date>
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