LS1023A in 16-bit data bus width configuration

SamCo — Fri, 03 Jun 2022 13:35:43 GMT

Hello,
We are designing a custom board based on a LS1023A with 2GB DDR4 + ECC (one bank).
We plan to connect and use this DDR memory with a 16-bit data bus witdh.
It seems to be OK by adjusting DDR_SDRAM_CFG[DBW] to '10b' as mentioned in the Reference Manual.
However, it is not clearly noted which data bus lanes we must use in this case : MDQ[15..0] or MDQ[31..16] ?
Regards,

Samuel

Re: LS1023A in 16-bit data bus width configuration

Pierre_Juste — Tue, 14 Jun 2022 13:00:18 GMT

The DDR data assignment of the bus data is proposed into document Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces, Rev. 2, 07/2019 page 4 Table 1. DDR4 design checklist (continued).

AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces - Application Note

Route all signals within a given byte lane on the same critical layer with the same via

count. Assuming ECC is used, the DDR4 data bus consists of nine data byte lanes.

NOTE: The byte ordering below is not a requirement; byte lanes can be routed in the

order that best fits the customer design.

Byte lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)
Byte lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS(1)
Byte lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS(2)
Byte lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS(3)
Byte lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS(4)
Byte lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS(5)
Byte lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS(6)
Byte lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS(7)
Byte lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)

To facilitate fan-out of the DDR4 data lanes (if needed), alternate adjacent data lanes

onto different critical layers (see Figure 1 and Figure 2).

NOTE: Some product implementations may only implement a 32-bit wide interface.

NOTE: If the device supports ECC, NXP highly recommends that the user implements

ECC on the initial hardware prototypes.

Additional information is proposed o application note QorIQ LS1043A Design Checklist , Rev. 6, 02/2021 page 18 in the note section.

AN5012, LS1043A Design Checklist - Application Note

Re: LS1023A in 16-bit data bus width configuration

yipingwang — Wed, 15 Jun 2022 03:26:27 GMT

if the DDR_SDRAM_CFG[DBW] = 2'b10 for 16-bit data bus configuration, the MDQ [0:15] will be used.
if the DDR_SDRAM_CFG[DBW] = 2'b01 for 32-bit data bus configuration, the MDQ [0:31] will be used.

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LS1023A in 16-bit data bus width configuration

Re: LS1023A in 16-bit data bus width configuration

Re: LS1023A in 16-bit data bus width configuration