topic Re: PCIe link downgrade issue with ls1021a in Layerscape

PCIe link downgrade issue with ls1021a

Anonymous — Mon, 18 Apr 2022 11:51:00 GMT

Running pci enum command in u-boot detects the gen3 device as gen1.

=> pci enum
PCIe0: pcie@3400000 Root Complex: x1 gen1
PCIe1: pcie@3500000 Root Complex: no link

Re: PCIe link downgrade issue with ls1021a

yipingwang — Tue, 19 Apr 2022 06:55:59 GMT

Which version LSDK are your using?

Would you please provide your whole u-boot console log?

Re: PCIe link downgrade issue with ls1021a

Anonymous — Tue, 19 Apr 2022 07:02:03 GMT

U-Boot SPL 2019.10+fsl+gde20a4439e (Apr 18 2022 - 12:53:00 +0000)
Trying to boot from MMC1

U-Boot 2019.10+fsl+gde20a4439e (Apr 18 2022 - 12:53:00 +0000)

CPU: Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
Clock Configuration:
CPU0(ARMV7):1200 MHz,
Bus:300 MHz, DDR:800 MHz (1600 MT/s data rate),
Reset Configuration Word (RCW):
00000000: 0608000c 00000000 00000000 00000000
00000010: 70000000 00007900 60040a00 21046000
00000020: 00000000 00000000 00000000 18000000
00000030: 00000000 841b7340 00000000 00000000
Model: LS1021A TWR Board
Board: LS1021ATWR
CPLD: V3.3
PCBA: V2.0
VBank: 0
DRAM: 1 GiB
Using SERDES1 Protocol: 112 (0x70)
si5341_clock_init: Cannot find udev for a bus 1
Flash: 128 MiB
MMC: FSL_SDHC: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

EEPROM: NXID v1
In: serial
Out: serial
Err: serial
SEC0: RNG instantiated
Net: eth0: ethernet@2d10000 [PRIME], eth1: ethernet@2d50000, eth2: ethernet@2d90000
Hit any key to stop autoboot: 0
=> pci enum
PCIe0: pcie@3400000 Root Complex: x1 gen1
PCIe1: pcie@3500000 Root Complex: no link

Re: PCIe link downgrade issue with ls1021a

yipingwang — Tue, 19 Apr 2022 07:06:13 GMT

Do you use u-boot from NXP LSDK? Which version?

Re: PCIe link downgrade issue with ls1021a

Anonymous — Tue, 19 Apr 2022 07:11:01 GMT

20.04

Re: PCIe link downgrade issue with ls1021a

yipingwang — Tue, 19 Apr 2022 09:56:54 GMT

Please refer to the following feature in LS1021ARM, PCIe gen 3 is not supported.

Re: PCIe link downgrade issue with ls1021a

Anonymous — Tue, 19 Apr 2022 10:02:46 GMT

I understand gen3 is not supported. But why is it getting detected as gen1. gen2 is supported right ?

Re: PCIe link downgrade issue with ls1021a

yipingwang — Fri, 29 Apr 2022 07:54:44 GMT

RCW[SRDS_DIV_PEX] is configure as "01".

0x Can train up to a max rate of 5 G

This is defect of LS1021ATWR u-boot, I will report it to the LSDK development team.

Re: PCIe link downgrade issue with ls1021a

Anonymous — Thu, 26 May 2022 12:14:10 GMT

Is there any update on this from the development team ?

Re: PCIe link downgrade issue with ls1021a

Anonymous — Thu, 26 May 2022 12:17:09 GMT

Is there any update on this issue from the development team ?