LayerscapeのトピックRe: QE / UCC UART on LS1088

QE / UCC UART on LS1088

mcbridematt — Fri, 29 Apr 2022 05:09:03 GMT

I'm trying to see if I can use the QUICC Engine (QE) on the LS1088A to get two extra four wire UARTs.

I'm not getting any characters in or out of either UC1/UC3 TXD/RXD

So far I have:

Set IRQ_EXT=2 so IRQ[3:9] is mapped to the UC1/UC3 UART functions
Set IIC4_EXT=3 so IIC4 SDA/SCL is mapped to UC1/UC3 CDB (carrier detect).
RCWSR12 reads back:
```
md 1e0012C 1
01e0012c: 02000600
```

Added this to fsl-ls1088a.dtsi, based on the content of fsl-ls1043a.dtsi. I changed the clock and IRQ settings as appropriate:

uqe: uqe@2400000 {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "qe";
	compatible = "fsl,qe", "simple-bus";
	ranges = <0x0 0x0 0x2400000 0x40000>;
	reg = <0x0 0x2400000 0x0 0x480>;
	brg-frequency = <150000000>; /* BRG is 1/2 of the QE bus frequency? */
	bus-frequency = <350000000>; /* QE gets 1/2 of the platform clock 700MHz */
	fsl,qe-num-riscs = <1>;
	fsl,qe-num-snums = <28>;
	status = "disabled";
	qeic: qeic@80 {
		compatible = "fsl,qe-ic";
		reg = <0x80 0x80>;
		#address-cells = <0>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	};
	si1: si@700 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,ls1043-qe-si",
				"fsl,t1040-qe-si";
		reg = <0x700 0x80>;
	};
	siram1: siram@1000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,ls1043-qe-siram",
				"fsl,t1040-qe-siram";
		reg = <0x1000 0x800>;
	};

	ucc1: ucc@2000 {
		cell-index = <1>;
		reg = <0x2000 0x200>;
		interrupts = <32>;
		interrupt-parent = <&qeic>;
	};

	ucc3: ucc@2200 {
		cell-index = <3>;
		reg = <0x2200 0x200>;
		interrupts = <34>;
		interrupt-parent = <&qeic>;
	};

	muram@10000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,qe-muram", "fsl,cpm-muram";
		ranges = <0x0 0x10000 0x6000>;
		data-only@0 {
				compatible = "fsl,qe-muram-data",
			"fsl,cpm-muram-data";
				reg = <0x0 0x6000>;
		};
	};
};

Added this to my device DTS:

&uqe {
	status = "okay";
	ucc@2000 {
		device_type = "serial";
		compatible = "ucc_uart";
		rx-clock-name = "brg1";
		tx-clock-name = "brg1";
		port-number = <0>;
	};
	ucc@2200 {
		device_type = "serial";
		compatible = "ucc_uart";
		rx-clock-name = "brg2";
		tx-clock-name = "brg2";
		port-number = <1>;
	};
};

Configured U-Boot to load the QE firmware:

Firmware 'Microcode version 0.0.1 for LS1021a r1.0' for 1021 V1.0
QE: uploading microcode 'Microcode for LS1021a r1.0' version 0.0.1

Applied the patch soc: fsl: qe: convert QE interrupt controller to platform_device on top of my kernel 5.10.112

In my kernel log I see:

[    1.532562] 2402000.ucc: ttyQE0 at MMIO 0x2402000 (irq = 107, base_baud = 9375000) is a QE
[    1.540926] ucc_uart 2402000.ucc: UCC1 assigned to /dev/ttyQE0
[    1.546898] 2402200.ucc: ttyQE1 at MMIO 0x2402200 (irq = 108, base_baud = 9375000) is a QE
[    1.555261] ucc_uart 2402200.ucc: UCC3 assigned to /dev/ttyQE1

For testing I have made sure the flow control is "disabled":

Pulled CDB for both UCC's to GND
Pulled RTSB to GND

I can send characters to the ttyQEx and it doesn't freeze, so I assume the QE firmware is working:

# stty -F /dev/ttyQE0
speed 9600 baud; line = 0;
-brkint -imaxbel
# echo "test" > /dev/ttyQE0
# echo "test" > /dev/ttyQE1

I can't see any signal activity on any of the UCx pins when characters are sent, and if I try to send characters to the RXD pin I don't see it either.

Is there something I am missing?

Re: QE / UCC UART on LS1088

yipingwang — Thu, 05 May 2022 08:27:57 GMT

In u-boot source code, please define the following options in include/configs/ls1088a_common.h.

CONFIG_U_QE

CONFIG_SYS_QE_FW_ADDR

In board/freescale/ls1088a/ls1088a.c, please define the following.

#ifdef CONFIG_U_QE
u_qe_init();
#endif

Please refer to ls1043ardb as an example.

Re: QE / UCC UART on LS1088

mcbridematt — Thu, 05 May 2022 09:15:41 GMT

As described above, I already modified my U-Boot to load the uQE binary.

Since my board is based on TF-A I changed U-Boot so I can supply the binary via the qe fw command which does:

qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
if (!u_qe_upload_firmware((const struct qe_firmware *)addr)) {
	out_be32(<qe_immr->iram.iready, QE_IRAM_READY);
	return CMD_RET_SUCCESS;
}

Any idea if my device tree settings (particularly bus/clock) is correct?

I could not find any device tree for the LS1088A with the uQE defined, so I made a guess based on the content of LS1088ARM.

Re: QE / UCC UART on LS1088

yipingwang — Mon, 09 May 2022 10:13:50 GMT

For UCC UART device tree definition, please refer to QE serial definition in arch/powerpc/boot/dts/fsl/p1025rdb.dtsi.

Re: QE / UCC UART on LS1088

mcbridematt — Wed, 18 May 2022 05:27:38 GMT

Still stuck on this.

I can verify that the uQE firmware has been loaded and is operational by reading out the microcode version register (CEURNR) and by checking the FLG semaphore after issuing QE commands.

I also configured BRGO2 to output on a pin and can see the output frequency about the same as the serial baud x16.

But:

I can't see any interrupts on the QE-IC (GIC 128)
In the UCC UART transmit sequence, the event and status register always read 0.

The lack of interrupts concern me the most, is there any easy way to cause a QE interrupt, preferably without any external pin output/input?