LayerscapeのトピックRe: Does the LS1046a support the Arm CoreLink CCI-400 Performance monitoring unit (PMU)?

Does the LS1046a support the Arm CoreLink CCI-400 Performance monitoring unit (PMU)?

Tonyx — Fri, 22 Apr 2022 03:02:59 GMT

Does the LS1046a support the Arm CoreLink CCI-400 Performance monitoring unit (PMU)?

The LS1046a RM manual mentions the "CCI-400 PMU", while it does not describe the registers of the "CCI-400 PMU". Note the "CCI-400 PMU" is not the PMU in Arm® Cortex®-A72 core.

The LS1046a RM manual mentions the "CCI-400 PMU"

section "1.4.2 Arm CoreLink CCI-400 Cache Coherent Interconnect" mentioned

"• Performance monitoring unit (PMU) to count performance-related events"

Section "9.6.3 Speculative fetch" mentioned

"You can use the PMU to record the number of retry transactions for each master interface."

LS1046A RM "9.5.1 CCI400 Registers memory map" doe not has the PMU register as in ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Revision: r1p5

3.3.6 Performance Monitor Control Register (PMCR)

3.3.17 Event Select Register

3.3.18 Event and Cycle Count Register

Re: Does the LS1046a support the Arm CoreLink CCI-400 Performance monitoring unit (PMU)?

yipingwang — Mon, 25 Apr 2022 03:21:44 GMT

LS1046a supports the Arm CoreLink CCI-400 Performance monitoring unit (PMU).

Please refer to the CCI-400 ARM document bundled with the LS1046ARM - ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Revision: r1p5 Technical Reference Manual.

There seems to be ambiguity in the LS1046ARM because CCI-400 has its own PMU.

Offset 0x90000 in the ARM CCI-400 TRM corresponds to the CCSR address 0x1180000 of the LS1046A.

Re: Does the LS1046a support the Arm CoreLink CCI-400 Performance monitoring unit (PMU)?

Tonyx — Tue, 26 Apr 2022 15:24:24 GMT

I did further test and be able to use the CCI-400 PMU on LS1046a .

Thanks!