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    <title>LayerscapeのトピックRe: LS1046A Kernel Panic (DDR Calibration Problem?)</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1046A-Kernel-Panic-DDR-Calibration-Problem/m-p/1443984#M10385</link>
    <description>&lt;P&gt;Please use QCVS DDRv tool to connect to your target board to do DDR validation and optimization.&lt;/P&gt;
&lt;P&gt;Please download and install CodeWarrior from the following link.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://drive.google.com/file/d/1Kjq1nLYrtIfWAHYrup5Cf-TTEJI9iWiu/view?usp=sharing" target="_blank"&gt;https://drive.google.com/file/d/1Kjq1nLYrtIfWAHYrup5Cf-TTEJI9iWiu/view?usp=sharing&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Please download&amp;nbsp;com.freescale.armv8.11.5.5.GA.Win.updatesite.210930.zip from the following link, open CodeWarrior IDE and install this service pack from&amp;nbsp;Help-&amp;gt;Install New Software-&amp;gt;Add-&amp;gt;Archive.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://drive.google.com/file/d/1ZHiYWDOhb27o0oD5Brqjn4_vJzRUCKoY/view?usp=sharing" target="_blank"&gt;https://drive.google.com/file/d/1ZHiYWDOhb27o0oD5Brqjn4_vJzRUCKoY/view?usp=sharing&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Then create a QCVS DDR project to connect to the target board to do optimization. Please refer to the attached user guide. If there is SPD on your target board, please create a project with "read from SPD" method.&lt;/P&gt;
&lt;P&gt;After get the optimized DDR configuration parameters, please use them to edit ATF source file&amp;nbsp;flexbuild_lsdk2012/packages/firmware/atf/plat/nxp/soc-ls1046/ls1046afrwy/ddr_init.c.&lt;/P&gt;</description>
    <pubDate>Thu, 14 Apr 2022 08:44:06 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2022-04-14T08:44:06Z</dc:date>
    <item>
      <title>LS1046A Kernel Panic (DDR Calibration Problem?)</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-Kernel-Panic-DDR-Calibration-Problem/m-p/1441714#M10362</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello, I am currently designing and testing based on LS1046FRWY board, but Kernel Panic has occurred, so I am inquiring.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The symptoms are not the initial sensors command, but when the cpu temperature is about 50 degrees Celsius, the following message appears when the reboot command is issued.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The system is currently under development with Fanless, and the problem below disappears when Fan is turned on, so I hope it becomes a reboot command even if the temperature rises (70 degrees Celsius or higher).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;We built another system based on LS1046a, and it was fine up to 75 degrees Celsius. But there's an unexpected problem with the newly developed system.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;So I suspect DDR Timing problem and we have NXP Code Warrior TAP product. I hope we can solve it through this.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;NOTICE: Fixed DDR on board&lt;/P&gt;&lt;P&gt;NOTICE: 4 GB DDR4, 64-bit, CL=15, ECC on&lt;BR /&gt;NOTICE: BL2: v1.5(release):LSDK-20.12-dirty&lt;BR /&gt;NOTICE: BL2: Built : 10:19:35, Apr 7 2022&lt;BR /&gt;NOTICE: BL31: v1.5(release):LSDK-20.12-dirty&lt;BR /&gt;NOTICE: BL31: Built : 10:19:35, Apr 7 2022&lt;BR /&gt;NOTICE: Welcome to LS1046 BL31 Phase&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;U-Boot 2020.04-dirty (Apr 07 2022 - 10:19:10 +0900)&lt;/P&gt;&lt;P&gt;SoC: LS1046AE Rev1.0 (0x87070010)&lt;BR /&gt;Clock Configuration:&lt;BR /&gt;CPU0(A72):1200 MHz CPU1(A72):1200 MHz CPU2(A72):1200 MHz&lt;BR /&gt;CPU3(A72):1200 MHz&lt;BR /&gt;Bus: 500 MHz DDR: 2100 MT/s FMAN: 700 MHz&lt;BR /&gt;Reset Configuration Word (RCW):&lt;BR /&gt;00000000: 0a15000c 0e000000 00000000 00000000&lt;BR /&gt;00000010: 11338888 00400016 60040000 c1000000&lt;BR /&gt;00000020: 00000000 00000000 00000000 00038800&lt;BR /&gt;00000030: 20044100 24003101 00000096 00000001&lt;BR /&gt;Model: LS1046A FRWY Board&lt;BR /&gt;Board: LS1046AFRWY-SATURN-HURA, Rev: B, boot from SD&lt;BR /&gt;SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ&lt;BR /&gt;DRAM: 3.9 GiB (DDR4, 64-bit, CL=15, ECC on)&lt;BR /&gt;SEC0: RNG instantiated&lt;BR /&gt;select_i2c_ch_pca9547: Cannot find udev for a bus 0&lt;BR /&gt;Using SERDES1 Protocol: 4403 (0x1133)&lt;BR /&gt;Using SERDES2 Protocol: 34952 (0x8888)&lt;BR /&gt;NAND: 0 MiB&lt;BR /&gt;MMC: FSL_SDHC: 0&lt;BR /&gt;Loading Environment from MMC... OK&lt;BR /&gt;EEPROM: Read failed.&lt;BR /&gt;In: serial&lt;BR /&gt;Out: serial&lt;BR /&gt;Err: serial&lt;BR /&gt;Net:&lt;BR /&gt;MMC read: dev # 0, block # 18432, count 128 ...&lt;BR /&gt;Fman1: Uploading microcode version 106.4.18&lt;BR /&gt;Could not get PHY for FSL_MDIO0: addr 1&lt;BR /&gt;Failed to connect&lt;BR /&gt;PCIe1: pcie@3400000 Root Complex: no link&lt;BR /&gt;PCIe2: pcie@3500000 disabled&lt;BR /&gt;PCIe3: pcie@3600000 disabled&lt;BR /&gt;FM1@DTSEC5, FM1@DTSEC6, FM1@TGEC1, FM1@TGEC2&lt;BR /&gt;Hit any key to stop autoboot: 0&lt;BR /&gt;switch to partitions #0, OK&lt;BR /&gt;mmc0 is current device&lt;BR /&gt;Scanning mmc 0:1...&lt;BR /&gt;Scanning mmc 0:2...&lt;BR /&gt;Found U-Boot script /ls1046afrwy_boot.scr&lt;BR /&gt;15431132 bytes read in 1017 ms (14.5 MiB/s)&lt;BR /&gt;do_fpgaload: fpga_load 15431132 bytes in 2721 ms&lt;BR /&gt;968 bytes read in 16 ms (58.6 KiB/s)&lt;BR /&gt;## Executing script at 80000000&lt;BR /&gt;37083648 bytes read in 2430 ms (14.6 MiB/s)&lt;BR /&gt;31419 bytes read in 17 ms (1.8 MiB/s)&lt;BR /&gt;## Flattened Device Tree blob at 90000000&lt;BR /&gt;Booting using the fdt blob at 0x90000000&lt;BR /&gt;Loading Device Tree to 000000008ffe5000, end 000000008ffffaba ... OK&lt;BR /&gt;WARNING failed to get smmu node: FDT_ERR_NOTFOUND&lt;BR /&gt;WARNING failed to get smmu node: FDT_ERR_NOTFOUND&lt;/P&gt;&lt;P&gt;Starting kernel ...&lt;/P&gt;&lt;P&gt;[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd082]&lt;BR /&gt;[ 0.000000] Linux version 5.4.47-dirty (root@hura-H81M-D2V) (gcc version 7.5.0 (Ubuntu/Linaro 7.5.0-3ubuntu1~18.04)) #1 SMP PREEMPT Thu Apr 7 10:03:32 KST 2022&lt;BR /&gt;[ 0.000000] Machine model: LS1046A FRWY Board&lt;BR /&gt;[ 0.000000] earlycon: uart8250 at MMIO 0x00000000021c0500 (options '')&lt;BR /&gt;[ 0.000000] printk: bootconsole [uart8250] enabled&lt;BR /&gt;[ 0.000000] efi: Getting EFI parameters from FDT:&lt;BR /&gt;[ 0.000000] efi: UEFI not found.&lt;BR /&gt;[ 0.000000] OF: reserved mem: initialized node qman-fqd, compatible id fsl,qman-fqd&lt;BR /&gt;[ 0.000000] OF: reserved mem: initialized node qman-pfdr, compatible id fsl,qman-pfdr&lt;BR /&gt;[ 0.000000] OF: reserved mem: initialized node bman-fbpr, compatible id fsl,bman-fbpr&lt;BR /&gt;[ 0.000000] cma: Reserved 320 MiB at 0x00000000e7c00000&lt;BR /&gt;[ 0.000000] NUMA: No NUMA configuration found&lt;BR /&gt;[ 0.000000] NUMA: Faking a node at [mem 0x0000000080000000-0x00000008ff7fffff]&lt;BR /&gt;[ 0.000000] NUMA: NODE_DATA [mem 0x8ff010800-0x8ff011fff]&lt;BR /&gt;[ 0.000000] Zone ranges:&lt;BR /&gt;[ 0.000000] DMA32 [mem 0x0000000080000000-0x00000000ffffffff]&lt;BR /&gt;[ 0.000000] Normal [mem 0x0000000100000000-0x00000008ff7fffff]&lt;BR /&gt;[ 0.000000] Movable zone start for each node&lt;BR /&gt;[ 0.000000] Early memory node ranges&lt;BR /&gt;[ 0.000000] node 0: [mem 0x0000000080000000-0x00000000fbdfffff]&lt;BR /&gt;[ 0.000000] node 0: [mem 0x0000000880000000-0x00000008fbffffff]&lt;BR /&gt;[ 0.000000] node 0: [mem 0x00000008ff000000-0x00000008ff7fffff]&lt;BR /&gt;[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ff7fffff]&lt;BR /&gt;[ 0.000000] psci: probing for conduit method from DT.&lt;BR /&gt;[ 0.000000] psci: PSCIv1.1 detected in firmware.&lt;BR /&gt;[ 0.000000] psci: Using standard PSCI v0.2 function IDs&lt;BR /&gt;[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.&lt;BR /&gt;[ 0.000000] psci: SMC Calling Convention v1.1&lt;BR /&gt;[ 0.000000] percpu: Embedded 24 pages/cpu s59928 r8192 d30184 u98304&lt;BR /&gt;[ 0.000000] Detected PIPT I-cache on CPU0&lt;BR /&gt;[ 0.000000] CPU features: detected: EL2 vector hardening&lt;BR /&gt;[ 0.000000] CPU features: kernel page table isolation forced ON by KASLR&lt;BR /&gt;[ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)&lt;BR /&gt;[ 0.000000] Speculative Store Bypass Disable mitigation not required&lt;BR /&gt;[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1001184&lt;BR /&gt;[ 0.000000] Policy zone: Normal&lt;BR /&gt;[ 0.000000] Kernel command line: console=ttyS0,115200 earlycon=uart8250,mmio,0x21c0500 root=PARTUUID=4052baa9-04 rw rootwait&lt;BR /&gt;[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)&lt;BR /&gt;[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)&lt;BR /&gt;[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off&lt;BR /&gt;[ 0.000000] ------------[ cut here ]------------&lt;BR /&gt;[ 0.000000] kernel BUG at /home/hura1/flexbuild_lsdk2012_ls1046_D1_2/packages/linux/linux/arch/arm64/kernel/acpi.c:284!&lt;BR /&gt;[ 0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP&lt;BR /&gt;[ 0.000000] Modules linked in:&lt;BR /&gt;[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.4.47-dirty #1&lt;BR /&gt;[ 0.000000] Hardware name: LS1046A FRWY Board (DT)&lt;BR /&gt;[ 0.000000] pstate: 80000185 (Nzcv dAIf -PAN -UAO)&lt;BR /&gt;[ 0.000000] pc : apei_claim_sea+0xc8/0x100&lt;BR /&gt;[ 0.000000] lr : apei_claim_sea+0x28/0x100&lt;BR /&gt;[ 0.000000] sp : ffffbfbb8a5736c0&lt;BR /&gt;[ 0.000000] x29: ffffbfbb8a5736c0 x28: ffffbfbb8a584b40&lt;BR /&gt;[ 0.000000] x27: 0000000000000000 x26: ffffbfbb8a09a008&lt;BR /&gt;[ 0.000000] x25: ffff00087f012200 x24: 0000000000000021&lt;BR /&gt;[ 0.000000] x23: 0000000060000185 x22: ffffbfbb884a0bb8&lt;BR /&gt;[ 0.000000] x21: ffffbfbb8a573750 x20: 0000000000000180&lt;BR /&gt;[ 0.000000] x19: ffffbfbb8a584b40 x18: ffffffffffffffff&lt;BR /&gt;[ 0.000000] x17: 0000000000018000 x16: 0000000000000000&lt;BR /&gt;[ 0.000000] x15: ffffbfbb8a579908 x14: 00000008ff03c000&lt;BR /&gt;[ 0.000000] x13: 0000000400000000 x12: 00000000000298bc&lt;BR /&gt;[ 0.000000] x11: 00000008ff012740 x10: 0000000400000000&lt;BR /&gt;[ 0.000000] x9 : 0000000000000000 x8 : ffff000066288000&lt;BR /&gt;[ 0.000000] x7 : 0000000000000000 x6 : 000000000000003f&lt;BR /&gt;[ 0.000000] x5 : 0000000080000000 x4 : 0000000000000000&lt;BR /&gt;[ 0.000000] x3 : 0000000080000000 x2 : ffff404cede74000&lt;BR /&gt;[ 0.000000] x1 : ffffbfbb8a584b40 x0 : 0000000000110002&lt;BR /&gt;[ 0.000000] Call trace:&lt;BR /&gt;[ 0.000000] apei_claim_sea+0xc8/0x100&lt;BR /&gt;[ 0.000000] do_sea+0x38/0x68&lt;BR /&gt;[ 0.000000] do_mem_abort+0x3c/0x98&lt;BR /&gt;[ 0.000000] el1_da+0x1c/0x90&lt;BR /&gt;[ 0.000000] do_sea+0x0/0x68&lt;BR /&gt;[ 0.000000] el1_da+0x1c/0x90&lt;BR /&gt;[ 0.000000] __rcu_read_unlock+0x0/0x190&lt;BR /&gt;[ 0.000000] __stack_chk_guard+0x0/0x8&lt;BR /&gt;[ 0.000000] Code: d5384113 b9401260 f90013b5 36a7fba0 (d4210000)&lt;BR /&gt;[ 0.000000] random: get_random_bytes called from print_oops_end_marker+0x48/0x68 with crng_init=0&lt;BR /&gt;[ 0.000000] ---[ end trace 0000000000000000 ]---&lt;BR /&gt;[ 0.000000] Kernel panic - not syncing: Fatal exception in interrupt&lt;/P&gt;</description>
      <pubDate>Mon, 11 Apr 2022 02:04:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-Kernel-Panic-DDR-Calibration-Problem/m-p/1441714#M10362</guid>
      <dc:creator>hyeonbin</dc:creator>
      <dc:date>2022-04-11T02:04:18Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A Kernel Panic (DDR Calibration Problem?)</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-Kernel-Panic-DDR-Calibration-Problem/m-p/1443984#M10385</link>
      <description>&lt;P&gt;Please use QCVS DDRv tool to connect to your target board to do DDR validation and optimization.&lt;/P&gt;
&lt;P&gt;Please download and install CodeWarrior from the following link.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://drive.google.com/file/d/1Kjq1nLYrtIfWAHYrup5Cf-TTEJI9iWiu/view?usp=sharing" target="_blank"&gt;https://drive.google.com/file/d/1Kjq1nLYrtIfWAHYrup5Cf-TTEJI9iWiu/view?usp=sharing&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Please download&amp;nbsp;com.freescale.armv8.11.5.5.GA.Win.updatesite.210930.zip from the following link, open CodeWarrior IDE and install this service pack from&amp;nbsp;Help-&amp;gt;Install New Software-&amp;gt;Add-&amp;gt;Archive.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://drive.google.com/file/d/1ZHiYWDOhb27o0oD5Brqjn4_vJzRUCKoY/view?usp=sharing" target="_blank"&gt;https://drive.google.com/file/d/1ZHiYWDOhb27o0oD5Brqjn4_vJzRUCKoY/view?usp=sharing&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Then create a QCVS DDR project to connect to the target board to do optimization. Please refer to the attached user guide. If there is SPD on your target board, please create a project with "read from SPD" method.&lt;/P&gt;
&lt;P&gt;After get the optimized DDR configuration parameters, please use them to edit ATF source file&amp;nbsp;flexbuild_lsdk2012/packages/firmware/atf/plat/nxp/soc-ls1046/ls1046afrwy/ddr_init.c.&lt;/P&gt;</description>
      <pubDate>Thu, 14 Apr 2022 08:44:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-Kernel-Panic-DDR-Calibration-Problem/m-p/1443984#M10385</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2022-04-14T08:44:06Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A Kernel Panic (DDR Calibration Problem?)</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-Kernel-Panic-DDR-Calibration-Problem/m-p/1444033#M10387</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I tried DDR Validation after listening to you. But here are the following symptoms.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;1. Using LSDK, the Linux login screen appears well.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2. The Codewarrier was connected to load the properties and tested through Validation, but some passed and some failed.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;- Pass : Stress test (Data is Address / Row hop read / SSM memcpy x32 / byte SSN memcpy x32 / Memcpy pseudo random data pattern / IRAM to ddr x32 / IRAM to ddr v2 x32)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;MemTester(Stuck Address / Random Value / Compare XOR / SUB / Mul / Div / Or / And / Sequential Increment / Solid Bit / Block Sequential / Checkerboard / Bit Spread / Bit Flip / Walkbits1 , 0),&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Read Margin, Read ODT and driver, Write ODT and driver, Operational DDR Test&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;- Fail : Centering the clock 0.12% Fail (WRLVL_START Searcher investigate HW issues on the board. / DDR interfaces is failing due to an issue other than WRLVL_START Values), Write Margin Fail 5.2% Fail(Change the test execution timeout parameter)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In the 'Centering the clock' item, Auto search &amp;amp; detect for write leveling start values, the value of the Search tab appears to be 0/1 and stops.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I also used an app called Stress to load it&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The Kernel Panic message appears at the kernel end when testing is performed through the 'stress --vm2 --vm-bytes 128M --timeout 2s' command, but PASS appears using the 'stress --vm2 --vm-bytes 1M --timeout 2s' command.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;So I think it's a hardware or artwork problem, but there seems to be no circuit problem. Can we solve this problem?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 14 Apr 2022 09:21:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-Kernel-Panic-DDR-Calibration-Problem/m-p/1444033#M10387</guid>
      <dc:creator>hyeonbin</dc:creator>
      <dc:date>2022-04-14T09:21:03Z</dc:date>
    </item>
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