topic Re: LS1046A Network problems in Layerscape

LS1046A Network problems

jack_huang1 — Wed, 06 Apr 2022 10:09:23 GMT

Dear:

The design of Ethernet part of our product refers to the network part of LS1046ARDB, and the configuration of SERDES is: 3333, 5A59. SGMII.2, SGMII.5, SGMII.6, SGMII.9, SGMII.10, and EC1 do not have external PHY devices, the connection mode is Mac to Mac. Sgmii.2 and EC1 are directly connected to marvell Switch (88E6320). Now there are some problems and confusion in the process of porting the Uboot. Details are as follows:

1. What is the purpose of the fsl_fman_ucode_LS1046_R1.0_108_4_9.bin file? Now fSL_fMAN_UCoDE_LS1046_R1.0_108_4_9.bin is written to the SD card as required. If the fsl_fman_UCode_LS1046_R1.0_108_4_9.bin file needs to be modified, how should I modify and compile it?

2. If you run the ping command in the uboot, the CPU resets. By printing log, suspected to be network driven function: Static int fm_eth_send(struct eth_device *dev, void *buf, int len), There is a problem with calling the functions muram_readw(u16 *addr) and muram_writew(u16 *addr, u16 val). Please analyze if this is the cause.

The following is the uboot print log and uboot map table.

U-Boot SPL 2018.09 (Apr 02 2022 - 15:10:11 +0800)

Initializing DDR....using SPD

total 4 GB

Trying to boot from MMC1

U-Boot 2018.09 (Apr 02 2022 - 15:10:11 +0800)

SoC: LS1046A Rev1.0 (0x87070110)

Clock Configuration:

CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz

CPU3(A72):1600 MHz

Bus: 600 MHz DDR: 1600 MT/s FMAN: 700 MHz

Reset Configuration Word (RCW):

00000000: 0c100010 0e000000 00000000 00000000

00000010: 33335a59 00805012 60040000 c1000000

00000020: 00000000 00000000 00000000 00018800

00000030: 20004500 05003101 00000096 00000001

Model: LS1046A FRWY Board

Board: LS1046AFRWY, Rev: A, boot from SD

SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ

I2C: ready

DRAM: 3.9 GiB (DDR4, 64-bit, CL=11, ECC on)

SEC0: RNG instantiated

FSL_SDHC: 0

ppa_init: fdt_check_header() failed

Waking secondary cores to start from fbd32000

All (4) cores are up.

Using SERDES1 Protocol: 13107 (0x3333)

Using SERDES2 Protocol: 23129 (0x5a59)

NAND: 0 MiB

MMC: Loading Environment from MMC... OK

In: serial

Out: serial

Err: serial

Net: MDIO_ADDR=1AFC000

MMC read: dev # 0, block # 18432, count 128 ...

Fman1: Uploading microcode version 108.4.9

*****fm_standard_init,99*****

PCIe0: pcie@3400000 Root Complex: no link

PCIe1: pcie@3500000 disabled

PCIe2: pcie@3600000 Root Complex: no link

FM1@DTSEC2 [PRIME], FM1@DTSEC3, FM1@DTSEC5, FM1@DTSEC6, FM1@DTSEC9, FM1@DTSEC10

Hit any key to stop autoboot: 0

=> ping 192.168.1.12

Using FM1@DTSEC2 device

"Synchronous Abort" handler, esr 0x96000004

elr: 000000008206bef4 lr : 0000000082041414 (reloc)

elr: 00000000fbd9def4 lr : 00000000fbd73414

x0 : 000000000000ffff x1 : 0000000000ffffff

x2 : 0000000000000110 x3 : 000000000000ffff

x4 : 0000000000000fff x5 : 0000000000000fff

x6 : 00000000000000ff x7 : 0000000000000000

x8 : 00000000fbc2d120 x9 : 000000000000000c

x10: 000000000000000a x11: 0000000000000006

x12: 000000000001869f x13: 0000000000001638

x14: 00000000fbc2d48c x15: 0000000000000002

x16: 0000000000002080 x17: 0000000000000002

x18: 00000000fbc2fd68 x19: 0000000000000000

x20: 00003ed5020180d2 x21: 00000000fbdac507

x22: 0000000000000001 x23: 0000000000000000

x24: 00000000fbc32240 x25: 000000000000002c

x26: 0000000000000002 x27: 00000000fbdef000

x28: 00000000fbdef000 x29: 00000000fbc2d200

Resetting CPU ...

resetting ...

U-boot SPL 2018.09 ,Please see Attachment 1.

Please see Attachment 2 for the hardware block diagram.

Re: LS1046A Network problems

yipingwang — Tue, 12 Apr 2022 09:32:31 GMT

1. No need to modify FMAN ucode.

FMan functions implemented thru microcode are the following:

A- ‘’Independent Mode’’

Simplified FMan-to-Memory model, bypassing BMan/QMan for Boot/Debug purposes and simple Ethernet driver

B- Table Lookup Coarse Classification

To classify incoming packets thru some protocol headers exact match criteria

C- Advanced packet processing offloads

Header manipulation, IP-Fragmentation/Reassembly, IPSec pre-processing

D- Host Command interface

QMan based FMan control commands used by core/SW for updating some FMan global configuration during operation.

2. Would you please provide board/freescale/ls1046ardb/eth.c?

Re: LS1046A Network problems

jack_huang1 — Wed, 13 Apr 2022 01:33:04 GMT

Hi，Yingping：

board/freescale/ls1046ardb/eth.c as follow：

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/io.h>
#include <netdev.h>
#include <fm_eth.h>
#include <fsl_dtsec.h>
#include <fsl_mdio.h>
#include <malloc.h>

#include "../common/fman.h"
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define RGMII_PHY3_ADDR 0x12

#define SGMII_PHY1_ADDR 0x3
#define SGMII_PHY2_ADDR 0x4
#define SGMII_PHY3_ADDR 0x11
#define SGMII_PHY4_ADDR 0x5
#define SGMII_PHY5_ADDR 0x6

#define FM1_10GEC1_PHY_ADDR 0x0
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
int i;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1, srds_s2;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;

/* 添加seds_s2初始化 */
srds_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;

dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
printf("MDIO_ADDR=%X\r\n",CONFIG_SYS_FM1_DTSEC_MDIO_ADDR);
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
/*
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
*/
/* Register the 10G MDIO bus */
/* fm_memac_mdio_init(bis, &tgec_mdio_info); */

/* Set the two on-board RGMII PHY address */
/* fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
*/

// fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY3_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY3_ADDR);
/* Set the two on-board SGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);

/* Set the on-board AQ PHY address */
// fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);

switch (srds_s1) {
// case 0x1133:
case 0x3333:
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY3_ADDR);
fm_info_set_phy_address(FM1_DTSEC9, SGMII_PHY4_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_PHY5_ADDR);
run_command("setenv serdes1 3333", 0);
break;
default:
printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
srds_s1);
break;
}

dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);

/* XFI on lane A, MAC 9 */
// dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
// fm_info_set_mdio(FM1_10GEC1, dev);
fm_info_set_mdio(FM1_DTSEC2, dev);

cpu_eth_init(bis);
#endif

return pci_eth_init(bis);
}

#ifdef CONFIG_FMAN_ENET
int fdt_update_ethernet_dt(void *blob)
{
u32 srds_s1;
int i, prop;
int offset, nodeoff;
const char *path;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;

/* Cycle through all aliases */
for (prop = 0; ; prop++) {
const char *name;

/* FDT might have been edited, recompute the offset */
offset = fdt_first_property_offset(blob,
fdt_path_offset(blob,
"/aliases")
);
/* Select property number 'prop' */
for (i = 0; i < prop; i++)
offset = fdt_next_property_offset(blob, offset);

if (offset < 0)
break;

path = fdt_getprop_by_offset(blob, offset, &name, NULL);
nodeoff = fdt_path_offset(blob, path);

switch (srds_s1) {
case 0x1133:
if (!strcmp(name, "ethernet0"))
fdt_status_disabled(blob, nodeoff);

if (!strcmp(name, "ethernet1"))
fdt_status_disabled(blob, nodeoff);
break;
default:
printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
__func__, srds_s1);
break;
}
}

return 0;
}
#endif

The attachment is the source file.

Thank you！

Re: LS1046A Network problems

yipingwang — Wed, 13 Apr 2022 09:42:04 GMT

DTSEC2 is PHY less interface, please don't assign PHY address for it, please delete the following line.

fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY3_ADDR);

Re: LS1046A Network problems

jack_huang1 — Thu, 14 Apr 2022 10:07:26 GMT

Hi, Yingping,

According to the suggestions in your email, ETH. C has been modified. After the test, it has no effect and ping cannot work. The latest progress of the project is as follows:

1. Now only CPU SGMII Mac2 is connected to Switch port1, and can be accessed through MDIO Switch;

2. Swtich shows a link, but the ping fails.

3. Check the statistics of Mac2 receiving and sending packets of Switch, and find that CPU only sends and does not receive packets.

Attached is the printed information of ping IP address.

Thank you!

Re: LS1046A Network problems

yipingwang — Mon, 25 Apr 2022 08:09:53 GMT

I have escalated this case to the SE team, please refer to the following update from them.

Because the issue is not able to be reproduced, could you identify which line inside the function is root cause of crash?

Re: LS1046A Network problems

nagurvalisayyad — Mon, 11 May 2026 04:45:29 GMT

Hi Yipingwang,

We are also facing the similar issue. How the issue is resolved.

Regards--

Nagurvali Sayyad.