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  <channel>
    <title>LayerscapeのトピックRe: Enable Quad Enable Bit in Status Register2  to enable Fast Read Quad Output (6Bh)</title>
    <link>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1441150#M10357</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Please apply the following codes to meet your need.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;index 08de2a2b4452..42a9d7cd20ab 100644&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;--- a/drivers/mtd/spi-nor/sfdp.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;+++ b/drivers/mtd/spi-nor/sfdp.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;@@ -264,7 +264,7 @@ static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; BFPT_DWORD(3), 16, /* Settings */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_PROTO_1_1_4,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; },&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;-&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;+#if 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; /* Fast Read 1-4-4 */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_HWCAPS_READ_1_4_4,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;@@ -272,7 +272,7 @@ static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; BFPT_DWORD(3), 0, /* Settings */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_PROTO_1_4_4,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; },&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;-&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;+#endif&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; /* Fast Read 4-4-4 */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_HWCAPS_READ_4_4_4,&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 08 Apr 2022 08:36:02 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2022-04-08T08:36:02Z</dc:date>
    <item>
      <title>Enable Quad Enable Bit in Status Register2  to enable Fast Read Quad Output (6Bh)</title>
      <link>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1429309#M10233</link>
      <description>&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;I am using LS1012A-FRWY and it has Winbond SPI flash w25q16dw.&lt;/P&gt;&lt;P&gt;I want to enable Quad Enable bit of Status register-2 in order to capture (6bh) Fast Read Quad Output instruction. I have access of mtd spi-nor driver.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Currently I tried below commands to generate the output and I am getting 0xeb command.&lt;/P&gt;&lt;P&gt;root@ls1012afrwy:~# mtd_debug read /dev/mtd0 0x0 100 dump_0x100&lt;BR /&gt;&lt;STRONG&gt;Copied 100 bytes from address 0x00000000 in flash to dump_0x100&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Is there any way to check the status of this Quad Enable bit?&lt;/P&gt;&lt;P&gt;Can you guide me the process that how to enable/disable Quad Enable bit for Winbond flash placed in NXP FRWYLS1012a or what changes I required to capture 6bh instruction?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;</description>
      <pubDate>Wed, 16 Mar 2022 14:09:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1429309#M10233</guid>
      <dc:creator>Maulik_Manvar</dc:creator>
      <dc:date>2022-03-16T14:09:54Z</dc:date>
    </item>
    <item>
      <title>Re: Enable Quad Enable Bit in Status Register2  to enable Fast Read Quad Output (6Bh)</title>
      <link>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1441150#M10357</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Please apply the following codes to meet your need.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;index 08de2a2b4452..42a9d7cd20ab 100644&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;--- a/drivers/mtd/spi-nor/sfdp.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;+++ b/drivers/mtd/spi-nor/sfdp.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;@@ -264,7 +264,7 @@ static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; BFPT_DWORD(3), 16, /* Settings */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_PROTO_1_1_4,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; },&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;-&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;+#if 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; /* Fast Read 1-4-4 */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_HWCAPS_READ_1_4_4,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;@@ -272,7 +272,7 @@ static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; BFPT_DWORD(3), 0, /* Settings */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_PROTO_1_4_4,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; },&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;-&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;+#endif&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; /* Fast Read 4-4-4 */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; SNOR_HWCAPS_READ_4_4_4,&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 08 Apr 2022 08:36:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1441150#M10357</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2022-04-08T08:36:02Z</dc:date>
    </item>
    <item>
      <title>Re: Enable Quad Enable Bit in Status Register2  to enable Fast Read Quad Output (6Bh)</title>
      <link>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1441248#M10358</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52411"&gt;@yipingwang&lt;/a&gt;&amp;nbsp; Thanks for your reply.&lt;/P&gt;</description>
      <pubDate>Fri, 08 Apr 2022 11:01:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1441248#M10358</guid>
      <dc:creator>Maulik_Manvar</dc:creator>
      <dc:date>2022-04-08T11:01:45Z</dc:date>
    </item>
    <item>
      <title>Re: Enable Quad Enable Bit in Status Register2  to enable Fast Read Quad Output (6Bh)</title>
      <link>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1705907#M13095</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52411"&gt;@yipingwang&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Above solution also helped me to generate 6Bh command.&lt;/P&gt;&lt;P&gt;When I am doing the similar kind of changes to generate quadspi 4-4-4 command and other dual spi command (1-2-2,1-1-2 or 2-2-2) it's not working as expected. Could you please help me to guide or by suggesting required changes to generate the other mode signals.&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Wed, 16 Aug 2023 15:53:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Enable-Quad-Enable-Bit-in-Status-Register2-to-enable-Fast-Read/m-p/1705907#M13095</guid>
      <dc:creator>yogeshdave07</dc:creator>
      <dc:date>2023-08-16T15:53:01Z</dc:date>
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