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    <title>topic Reset Scheme LS1012A in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/Reset-Scheme-LS1012A/m-p/1415328#M10072</link>
    <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I have designed a board based on LS1012A processor. I have decided to drop the K20 microcontroller (USB to JTAG Bridge) and access the processor directly through JTAG interface.&amp;nbsp;&lt;/P&gt;&lt;P&gt;We need clarification on following:&lt;/P&gt;&lt;P&gt;1. There are two resets for LS1012A, One for Microprocessor ("POR") and other reset "TRST" for JTAG Interface (TAP Controller).&lt;/P&gt;&lt;P&gt;2. For "POR" there are three resets used:&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;a. Power Good Signal from PMIC&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;b. Reset from JTAG Connector&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;c. Reset Request from LS1012A itself.&lt;/P&gt;&lt;P&gt;3. For "TRST", we are considering below:&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;a. Power Good Signal from PMIC only&lt;/P&gt;&lt;P&gt;Query: Do we also consider the Reset from the JTAG Header for "TRST" of LS1012A.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kindly provide the reset scheme for LS1012A in case we only need to debug through JTAG.&lt;/P&gt;&lt;P&gt;Reference Board referred: "XFRWY-LS1012A-PA Rev - B"&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Reshmi&lt;/P&gt;</description>
    <pubDate>Thu, 17 Feb 2022 13:20:23 GMT</pubDate>
    <dc:creator>g_reshmi</dc:creator>
    <dc:date>2022-02-17T13:20:23Z</dc:date>
    <item>
      <title>Reset Scheme LS1012A</title>
      <link>https://community.nxp.com/t5/Layerscape/Reset-Scheme-LS1012A/m-p/1415328#M10072</link>
      <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I have designed a board based on LS1012A processor. I have decided to drop the K20 microcontroller (USB to JTAG Bridge) and access the processor directly through JTAG interface.&amp;nbsp;&lt;/P&gt;&lt;P&gt;We need clarification on following:&lt;/P&gt;&lt;P&gt;1. There are two resets for LS1012A, One for Microprocessor ("POR") and other reset "TRST" for JTAG Interface (TAP Controller).&lt;/P&gt;&lt;P&gt;2. For "POR" there are three resets used:&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;a. Power Good Signal from PMIC&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;b. Reset from JTAG Connector&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;c. Reset Request from LS1012A itself.&lt;/P&gt;&lt;P&gt;3. For "TRST", we are considering below:&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;a. Power Good Signal from PMIC only&lt;/P&gt;&lt;P&gt;Query: Do we also consider the Reset from the JTAG Header for "TRST" of LS1012A.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kindly provide the reset scheme for LS1012A in case we only need to debug through JTAG.&lt;/P&gt;&lt;P&gt;Reference Board referred: "XFRWY-LS1012A-PA Rev - B"&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Reshmi&lt;/P&gt;</description>
      <pubDate>Thu, 17 Feb 2022 13:20:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Reset-Scheme-LS1012A/m-p/1415328#M10072</guid>
      <dc:creator>g_reshmi</dc:creator>
      <dc:date>2022-02-17T13:20:23Z</dc:date>
    </item>
    <item>
      <title>Re: Reset Scheme LS1012A</title>
      <link>https://community.nxp.com/t5/Layerscape/Reset-Scheme-LS1012A/m-p/1415493#M10073</link>
      <description>&lt;P&gt;&amp;gt; Do we also consider the Reset from the JTAG Header for "TRST" of LS1012A?&lt;/P&gt;
&lt;P&gt;No.&lt;/P&gt;
&lt;P&gt;Refer to the AN5192 - QorIQ LS1012A Design Checklist, Figure 17. JTAG interface connection.&lt;/P&gt;</description>
      <pubDate>Thu, 17 Feb 2022 17:41:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Reset-Scheme-LS1012A/m-p/1415493#M10073</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2022-02-17T17:41:30Z</dc:date>
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