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    <title>topic ROM routines + 908QT2 in 8-bit Microcontrollers</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/ROM-routines-908QT2/m-p/123973#M94</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;SPAN style="color: #ff0000;"&gt;This message contains an entire topic ported from a separate forum. The original message and all replies are in this single message. We have seeded this new forum with selected information that we expect will be of value to you as you search for answers to your questions.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;Thu Sep 22, 2005 8:03 pm&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;Hey all.&lt;BR /&gt;&lt;BR /&gt; Has anyone successfully used the ROM-resident routines in a 908QT2 MCU? I've done all my development with a DEMO908QB8 board, using the AN2635 as a reference for the ROM routine locations, and using AN2504 and the Metrowerks programming API. Wonderful tools, I might add, with the exception of one error in the API (MASS bit mask was wrong).&lt;BR /&gt;&lt;BR /&gt; I got all three of the functions I needed working on the Demo board - ReadRange, ProgramRangX, and ErasePageX.&lt;BR /&gt;&lt;BR /&gt; In porting this code into my target MCU, a 908QT2, I've been unable to get the ROM routines to work. I've updated the initialization (ROM routine locations are the same) for the new target, using FAQ-20979 and AN2346. It's difficult since there is no way to debug my target code on this MCU. But I've narrowed it down. My program never returns from the ROM subroutines. This has got to be setup, right?&lt;BR /&gt;&lt;BR /&gt; Key differences (that I can find) between the QB8 and QT2 are:&lt;BR /&gt;&lt;BR /&gt; memory map and size, obviously&lt;BR /&gt; CPUSPD value ($04 on the QB8, $13 on the QT2)&lt;BR /&gt;&lt;BR /&gt; Is there something else I'm missing?&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Sat Sep 24, 2005 7:03 am&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;I have successfully used the ERARNGE ($2806) and PRGRNGE ($2809) ROM-resident routines for the QT/QY series. I initially used AN2346 for ideas, but found these routines more complex than were necessary for my intended application. So the adapted routine that resulted will erase the first page (64 bytes) of flash, and then program up to 32 bytes. This is satisfactory for small amounts of data that only need to change a few times, so flash endurance is not a problem.&lt;BR /&gt;&lt;BR /&gt; For the code shown below, I have defined the R0M routine locations, plus the following registers within an include file:&lt;BR /&gt;&lt;BR /&gt; CTRLBYT EQU RAM+8&lt;BR /&gt; CPUSPD EQU RAM+9&lt;BR /&gt; LADDR EQU RAM+10&lt;BR /&gt; FLBPR EQU $FFBE&lt;BR /&gt;&lt;BR /&gt; Here is the code for the sub-routine. Note that interrupts must be re-enabled because ERARNGE disables them.&lt;BR /&gt;&lt;BR /&gt; ; GENERAL EQUATES:&lt;BR /&gt; PBLOCK EQU FLASH ; Non-volatile block for data&lt;BR /&gt; DATSIZE EQU 2 ; Data bytes to be stored (up to 32)&lt;BR /&gt; FLBPRVAL EQU {(FLASH-$C000)/$40+1} ; Unprotect first block&lt;BR /&gt; SPDVAL EQU 13 ; ~(3.2 * 4) for 3.2MHz bus&lt;BR /&gt;&lt;BR /&gt; ***********************************************************&lt;BR /&gt; * ERASE FLASH PAGE &amp;amp; WRITE BLOCK&lt;BR /&gt; ***********************************************************&lt;BR /&gt; ; On entry, data to be written must reside in RAM, starting at RAM+12.&lt;BR /&gt; ; RAM+8 through to RAM+11 will be over-written.&lt;BR /&gt; ; On exit, CF = 1 if programmed data is verified, otherwise CF = 0&lt;BR /&gt;&lt;BR /&gt; WRBLOCK:&lt;BR /&gt; MOV #SPDVAL,CPUSPD&lt;BR /&gt; CLR CTRLBYT ; Page erase only&lt;BR /&gt; LDHX #PBLOCK&lt;BR /&gt; LDA #DATSIZE&lt;BR /&gt; PSHX&lt;BR /&gt; ADD 1,SP ; Add LS address&lt;BR /&gt; DECA ; Last position in block&lt;BR /&gt; TAX&lt;BR /&gt; STHX LADDR&lt;BR /&gt; PULX&lt;BR /&gt; JSR ERARNGE ; Erase range - disable interrupts&lt;BR /&gt; LDHX #PBLOCK&lt;BR /&gt; JSR PRGRNGE ; Program block&lt;BR /&gt; CLI ; Re-enable interrupts&lt;BR /&gt; RTS&lt;BR /&gt;&lt;BR /&gt; ***********************************************************&lt;BR /&gt; ORG FLBPR ; Flash block protect register&lt;BR /&gt; DB FLBPRVAL ; First flash block unprotected&lt;BR /&gt;&lt;BR /&gt; I hope this helps with your problem.&lt;BR /&gt;&lt;BR /&gt; Regards,&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Sep 26, 2005 11:28 pm&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Thanks a bunch! I'll study your assembly and compare it with my C code. There's got to be some significant difference. Stay tuned...&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Fri Oct 21, 2005 5:11 pm&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Well, I found out what was wrong with my code. It was the RDVRGNG routine that my program never returned from on my QT2/4 target. Yet RDVRGNG works on my QB8 DEMO board.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;BR /&gt;Apparently the ROM routine in this latest QT mask is different in how it fills up the RAM with Flash data. Both ERARNGE and PRGRNGE are working fine for me. I've replaced the RDVRGNG with my own routine to retrieve the flash data into local RAM.&lt;BR /&gt;&lt;BR /&gt; I wonder if the location in ROM for RDVRGNG is different now, or just radically structured differently?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 25 Jan 2006 01:49:54 GMT</pubDate>
    <dc:creator>RChapman</dc:creator>
    <dc:date>2006-01-25T01:49:54Z</dc:date>
    <item>
      <title>ROM routines + 908QT2</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/ROM-routines-908QT2/m-p/123973#M94</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;SPAN style="color: #ff0000;"&gt;This message contains an entire topic ported from a separate forum. The original message and all replies are in this single message. We have seeded this new forum with selected information that we expect will be of value to you as you search for answers to your questions.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;Thu Sep 22, 2005 8:03 pm&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;Hey all.&lt;BR /&gt;&lt;BR /&gt; Has anyone successfully used the ROM-resident routines in a 908QT2 MCU? I've done all my development with a DEMO908QB8 board, using the AN2635 as a reference for the ROM routine locations, and using AN2504 and the Metrowerks programming API. Wonderful tools, I might add, with the exception of one error in the API (MASS bit mask was wrong).&lt;BR /&gt;&lt;BR /&gt; I got all three of the functions I needed working on the Demo board - ReadRange, ProgramRangX, and ErasePageX.&lt;BR /&gt;&lt;BR /&gt; In porting this code into my target MCU, a 908QT2, I've been unable to get the ROM routines to work. I've updated the initialization (ROM routine locations are the same) for the new target, using FAQ-20979 and AN2346. It's difficult since there is no way to debug my target code on this MCU. But I've narrowed it down. My program never returns from the ROM subroutines. This has got to be setup, right?&lt;BR /&gt;&lt;BR /&gt; Key differences (that I can find) between the QB8 and QT2 are:&lt;BR /&gt;&lt;BR /&gt; memory map and size, obviously&lt;BR /&gt; CPUSPD value ($04 on the QB8, $13 on the QT2)&lt;BR /&gt;&lt;BR /&gt; Is there something else I'm missing?&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Sat Sep 24, 2005 7:03 am&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;I have successfully used the ERARNGE ($2806) and PRGRNGE ($2809) ROM-resident routines for the QT/QY series. I initially used AN2346 for ideas, but found these routines more complex than were necessary for my intended application. So the adapted routine that resulted will erase the first page (64 bytes) of flash, and then program up to 32 bytes. This is satisfactory for small amounts of data that only need to change a few times, so flash endurance is not a problem.&lt;BR /&gt;&lt;BR /&gt; For the code shown below, I have defined the R0M routine locations, plus the following registers within an include file:&lt;BR /&gt;&lt;BR /&gt; CTRLBYT EQU RAM+8&lt;BR /&gt; CPUSPD EQU RAM+9&lt;BR /&gt; LADDR EQU RAM+10&lt;BR /&gt; FLBPR EQU $FFBE&lt;BR /&gt;&lt;BR /&gt; Here is the code for the sub-routine. Note that interrupts must be re-enabled because ERARNGE disables them.&lt;BR /&gt;&lt;BR /&gt; ; GENERAL EQUATES:&lt;BR /&gt; PBLOCK EQU FLASH ; Non-volatile block for data&lt;BR /&gt; DATSIZE EQU 2 ; Data bytes to be stored (up to 32)&lt;BR /&gt; FLBPRVAL EQU {(FLASH-$C000)/$40+1} ; Unprotect first block&lt;BR /&gt; SPDVAL EQU 13 ; ~(3.2 * 4) for 3.2MHz bus&lt;BR /&gt;&lt;BR /&gt; ***********************************************************&lt;BR /&gt; * ERASE FLASH PAGE &amp;amp; WRITE BLOCK&lt;BR /&gt; ***********************************************************&lt;BR /&gt; ; On entry, data to be written must reside in RAM, starting at RAM+12.&lt;BR /&gt; ; RAM+8 through to RAM+11 will be over-written.&lt;BR /&gt; ; On exit, CF = 1 if programmed data is verified, otherwise CF = 0&lt;BR /&gt;&lt;BR /&gt; WRBLOCK:&lt;BR /&gt; MOV #SPDVAL,CPUSPD&lt;BR /&gt; CLR CTRLBYT ; Page erase only&lt;BR /&gt; LDHX #PBLOCK&lt;BR /&gt; LDA #DATSIZE&lt;BR /&gt; PSHX&lt;BR /&gt; ADD 1,SP ; Add LS address&lt;BR /&gt; DECA ; Last position in block&lt;BR /&gt; TAX&lt;BR /&gt; STHX LADDR&lt;BR /&gt; PULX&lt;BR /&gt; JSR ERARNGE ; Erase range - disable interrupts&lt;BR /&gt; LDHX #PBLOCK&lt;BR /&gt; JSR PRGRNGE ; Program block&lt;BR /&gt; CLI ; Re-enable interrupts&lt;BR /&gt; RTS&lt;BR /&gt;&lt;BR /&gt; ***********************************************************&lt;BR /&gt; ORG FLBPR ; Flash block protect register&lt;BR /&gt; DB FLBPRVAL ; First flash block unprotected&lt;BR /&gt;&lt;BR /&gt; I hope this helps with your problem.&lt;BR /&gt;&lt;BR /&gt; Regards,&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Sep 26, 2005 11:28 pm&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Thanks a bunch! I'll study your assembly and compare it with my C code. There's got to be some significant difference. Stay tuned...&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Fri Oct 21, 2005 5:11 pm&lt;/STRONG&gt;&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Well, I found out what was wrong with my code. It was the RDVRGNG routine that my program never returned from on my QT2/4 target. Yet RDVRGNG works on my QB8 DEMO board.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;BR /&gt;Apparently the ROM routine in this latest QT mask is different in how it fills up the RAM with Flash data. Both ERARNGE and PRGRNGE are working fine for me. I've replaced the RDVRGNG with my own routine to retrieve the flash data into local RAM.&lt;BR /&gt;&lt;BR /&gt; I wonder if the location in ROM for RDVRGNG is different now, or just radically structured differently?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Jan 2006 01:49:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/ROM-routines-908QT2/m-p/123973#M94</guid>
      <dc:creator>RChapman</dc:creator>
      <dc:date>2006-01-25T01:49:54Z</dc:date>
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