topic Re: SH8 timer channel value registers in 8-bit Microcontrollers

SH8 timer channel value registers

RobG — Mon, 19 May 2008 11:05:35 GMT

I am trying to get the SH8 to do PWM.

In SH8 the following does not change the timer value registers.

ldhx #a_number ; any 16 bit value

sthx $0029 ; TPM1C1VH or any other timer channel value register.

Writing to TPM1MODH does write ok. I get timer overflow interupts ok for period but can't set pulse width since I can't get a value other than 0 in TPM1C1VH.

However if I do the same in QG8 it does work eg;

ldhx #a_number ; any 16 bit value

sthx $0049 ; TPMC1VH or any other timer channel value register

I'm using WinIDE, ProgHCS08 and ICDHCS08 debugger, Cyclone Pro as interface.

Testing the device as standalone circuit or via ICDHCS08 shows the same result.

I've tried a couple of SH8 chips.

With any luck this will be simple and something I'm overlooking. Perhaps a memory mapping problem??

Rob

Re: SH8 timer channel value registers

Ake — Mon, 19 May 2008 15:35:51 GMT

Hi,

The QC8 has a TPMV2 and the SH8 has got the TPMV3.

I have not studied your code to find what the reason is, but I believe that the V2/V3 difference is the reason.

Regards,

Ake

Re: SH8 timer channel value registers

RobG — Mon, 19 May 2008 20:21:32 GMT

Found it! Yes it is due to differences between TPMV2 and TPMV3. In TPMV3 writes to the channel value registers are not recognised unless the channel has been configured for output compare first. I was attempting to write the pulse width value to the channel value register before configuring the channel as output compare. That works ok in TPMV2 but not TPMV3.

Rob

Re: SH8 timer channel value registers

MplsMan — Sat, 26 Jul 2008 02:26:31 GMT

Actually, on the TPMV3 (as opposed to the TPMV2), you need to be careful that you do not immediately write to the TPMxCnSC register after updating the value in TPMxCnVH:TPMxCnVL. The channel value registers are not immediately loaded in the TPMV3 (in OC or PWM mode), but are rather held in a coherency buffer until the next TPM clock tick. So even if the channel had previously been configured as an Output Compare (or PWM for that matter), the culprit may have been a subsequent access to the corresponding status and control register. Although it was OK to update the channel value (TPMxCnVH:TPMxCnVL) and then clear the interrupt flag (within TPMxCnSC) on the TPMV2, that register update sequence may prevent the channel value from actually being updated on TPM3. Here is description from Freescale as provided within some of the 9S08AC manuals and application notes:

In output compare or PWM mode, writing to TPMxCnSC (after writing to the channel value registers, TPMxCnVH:TPMxCnVL, but before they are updated) cancels the write to TPMxCnVH:TPMxCnVL and leaves the register values unchanged.

This is particularly relevant for the AC60 because, depending upon the configuration of CLKS and the selected mode, there could be a considerable time before registers TPMxCnVH:TPMxCnVL are updated. It is, therefore, important to ensure TPMxCnSC is not written during this time unless you want to cancel a previous write to the channel value registers.

As a result of these differences in the latching mechanism, you may have to initialise the timer registers in a different order than before to allow for this.