Updating TPMxCnV while CHnIE enabled (BUG?)

JackyRyan — Thu, 29 Oct 2020 08:58:46 GMT

Hey everyone,

I've got a strange problem in updating the TPM value registers and didn't found a solution yet. I read the datasheet of MC9S08DZ60 the nth time, looked for the errata sheet (3M05C) and of course searched in this forum but can't find exactly the same issue.

When I want to set up a EPWM with TPM1 on HCS08DZ60 and the channel interrupt is disabled (CHnIE = 0) but with timer overflow interrupt enabled (TOI = 1) I can set the TPM1CnV whenever I want to and the value is written to the register. But when I enable the channel interrupt I recognized that the value registers TPM1CnV are not updated although I wrote them. After some debugging I found out that the value is only written to TPM1CnV when TPM1CNT > TPM1CnV at the time I want to write to it. So when the pwm duty cycle is close to 100% the probability is very low to be between TPM1CnV and TPM1MOD to update the value.

I tried to set the value registers in endless loop of main() and to set it in the interrupt what makes no difference. I did the tpm1 overflow and channel interrupt acknowledge as described in datasheet and proposed by processor expert, e.g.

=> TPM1C3SC &=0x7F; or

=> (void)getReg8(TPM1C3SC); clrReg8Bits(TPM1C3SC, 0x80);

so it IS a two step sequence of reading and then writing the zero

So, what do I wrong? It's a fact, that when disabling CHnIE I can set the TPMxCnV whenever I want!

In datasheet section 16.3.5 it says:

"If (CLKSB:CLKSA not = 0:0 and in EPWM orCPWM modes), then the registers are updated after
the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1)
to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is
made when the TPM counter changes from 0xFFFE to 0xFFFF."

I cannot see any reason why the values are not written. Here the register settings:

// 1. Setting TPM1C3SC
TPM1C3SC = 0x68;

// 2. Setting TPM1SC (depending on desired frequency)
TPM1SC = 0x48;

// 3. Setting TPM1MOD (depending on desired frequency)
TPM1MOD = 40000;

// 4. Setting TPM1C3V
TPM1C3V = 20000;

Setting TPM1C3V the first time is always succesful because it's zero. Writing a zero when it has a value > 0 is always succesful, too!!

Hope to get an idea from you!

Thanks in advance,

Daniel

Re: Updating TPMxCnV while CHnIE enabled (BUG?)

zdenojanoska — Sat, 10 Dec 2011 06:02:44 GMT

Waw, 2 years old post without any response?

My 9S08SG8 behaves totally the same. All one day I've read the manual.

So the only choice is write the TPM1C0V in overflow interrupt when Ch0 interrupt is disable??? Where is the problem???

Is there someone with the same error?

Have a nice day.

8-bit MicrocontrollersのトピックUpdating TPMxCnV while CHnIE enabled (BUG?)

Updating TPMxCnV while CHnIE enabled (BUG?)

Re: Updating TPMxCnV while CHnIE enabled (BUG?)