8-bit MicrocontrollersのトピックRe: QE128 Timer problem

QE128 Timer problem

Kaare — Mon, 09 Nov 2009 19:15:51 GMT

I have a weird problem with the MC9S08QE128 device and timer operation.

I want to use a timer as a PWM output so i do it like this:

// Set PWM to BUSCLK and prescaler to 0

TPM1SC = 0x08;

// Edge-aligned PWM, High-true pulses

TPM1C2SC = 0x28;

// Set the period

TPM1MOD = 32000;

// Set the duty cycle to 50%

TPM1C2V = 16000;

However the above code does not change the Modulo or the dutycycle the first time it is run. I need to run the above code block twice to get it to set the TPM1MOD and TPM1C2V registers and i need to wait at least 10mS between the two writes for it to work. Why is that?

Also, i use an external 32.768 Khz crystal and the bus is set to run at 20MHz. When i measure on the above mentioned output, it takes aprox. 2.5 seconds before the pwm is available from when i hit Run in the debugger.

Message Edited by Kaare on 2009-11-09 12:41 PM

Re: QE128 Timer problem

tonyp — Mon, 09 Nov 2009 20:02:18 GMT

From Peripheral Quick Reference Guide:

Configuring the TPM to generate PWM signals with common duty cycles is straightforward:
1. Load the desired period for all channels on the base timer TPMMOD register.
2. Load the desired duty cycle for each channel on the TPMCnV registers.
3. Select the PWM functionality for each channel that will be used to generate PWM by using the
TPMCnSC register of each channel.
4. Select the PWM mode, input clock and prescaler for the main timer in the TPMSC register.

Try this order of initialization (TPMMOD first, and TPMSC last). The way you do it, it's possible the settings don't take effect until after the current period expires, which might explain the 2.5 sec delay (just guessing).

Message Edited by tonyp on 2009-11-09 02:04 PM

Re: QE128 Timer problem

Kaare — Mon, 09 Nov 2009 20:57:59 GMT

Hi Tony

I tried your recommendation but it doesn't change anything. Another solution that works is this:

while(TPM1MOD != frequency) TPM1MOD = frequency;

and the same with TPM1C2V.

Re: QE128 Timer problem

bigmac — Tue, 10 Nov 2009 01:20:29 GMT

Hello,

As TonyP has already pointed out, is important to set the CLKSB:CLKSA bits of the TPM1SC register after the TPM1MOD and the TPM channel registers have been set up, in order to avoid a delay of a full TPM overflow cycle in free running mode. Here is an extract from the datasheet.

Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF.

Similar considerations also apply to the update of the channel registers -

In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written.
• If (CLKSB:CLKSA not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the TPM counter (end of the prescaler counting).
• If (CLKSB:CLKSA not = 0:0 and in EPWM or CPWM modes), then the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF.

Even if the update of the TPM1MOD and channel registers occurs while CLKSB:CLKSA = 0:0, the PWM output signal will not commence until the first modulo overflow occurs. Perhaps you are not waiting a sufficient time for the changes to take effect.

As to the initial 2.5 second delay, this is probably due to the start-up delay of the low frequency crystal. The oscillation amplitude will slowly build up to the normal operating level, and then there will be a further delay until the FLL locks. Higher frequency crystals will have considerably shorter start-up delay.

Regards,

Mac

Re: QE128 Timer problem

Kaare — Tue, 10 Nov 2009 17:40:17 GMT

Hello bigmac and thanks for your response.

However the problem is not that it waits a full overflow cycle, but that it never sets the registers at all if i only set them once. If i break somewhere in my code in the debugger and the do TPM3C2V = 0xfafa for example, then the register is not written. If i manually find the adress in the memory window and edit the register there, then it works.

The only way i can get it to change the timer registers is by doing the above mentioned while-loop. But if i do that, then the code gets trapped there if i debug the application as the condition never gets true.

Re: QE128 Timer problem

bigmac — Wed, 11 Nov 2009 00:09:04 GMT

Hello,

Do you get the correct PWM output if you don't try to debug the writing of the TPM registers? My understanding is that the TPM coherency mechanism operates differently in BDM mode.

Regards,

Mac