topic QE128 - ICS ver.3 default setting, where do half the frequency go? in 8-bit Microcontrollers

QE128 - ICS ver.3 default setting, where do half the frequency go?

Tbspd_TOK — Wed, 04 Feb 2009 15:05:44 GMT

As said in the heading, I try to find out where half the systemclock go in the HCS08QE128.

The ICS is set as reset default in FEI mode, BDIV=01 or /2, RDIV=0 or /1. DRS=00, DMX32=0 -> FLL factor =512. Frequency is 31250Hz

From this I get the frequency to be (31250*512)/1/2=8MHZ, but the correct answer is 4MHz.

In the previous version of the ICS the DCO output is apparently divided by 2. But this is not specified in the version 3 of the ICS. Is this the reason for the half frequency?

I have studied the QE128 reference manual and the 'HCS08 Unleashed Designer's guide' but I can't figure any logical reason for the difference.

Could anyone put me in the correct direction for some further documentation?

TOK

Message Edited by Tbspd_TOK on 2009-02-04 07:07 AM

Re: QE128 - ICS ver.3 default setting, where do half the frequency go?

bigmac — Wed, 04 Feb 2009 19:46:06 GMT

Hello TOK,

You do not mention whether you have set the BDIV value within ICSC2 register. The reset default will divide the DCO output by 2, and then there is a further divide by 2 from ICSOUT to the bus clock. You will need to change BDIV from the reset value to achieve the higher bus frequency.

Regards,
Mac

Re: QE128 - ICS ver.3 default setting, where do half the frequency go?

Tbspd_TOK — Wed, 04 Feb 2009 20:08:27 GMT

Mac

Thanks for your answer.

The problem is the ICSOUT divide by 2 before the busclock. I tried to look at some tutorials, and there it was described, but I could not find it in the Reference Manual for QE128(rev2).

It could be a good idea to include it in the ICS chapter, under 'Features'.

TOK

Re: QE128 - ICS ver.3 default setting, where do half the frequency go?

peg — Thu, 05 Feb 2009 04:08:46 GMT

Hi TOK,

I haven't looked at the manual, but this is always the case with at least S08's (that the ICSCLK is double that of the BUSCLK) Also note that ICSCLK = CPUCLK even though timing is measured in BUSCLK's.
These details are always a little vague in the datasheets.

Re: QE128 - ICS ver.3 default setting, where do half the frequency go?

bigmac — Thu, 05 Feb 2009 07:30:34 GMT

Hello TOK,

Refer to Fig. 1.2 "System Clock Distribution Diagram" within the Reference Manual for the 'QE128.

Regards,
Mac