<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>8-bit MicrocontrollersのトピックXCLK on QG4/8</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143727#M6678</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Ok, I read the datasheet, I looked at AN3041, and even some of the code&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;exmaples, but I'm still confused.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;XCLK is the "fixed frequency clock" selectable as inputs to the timers,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and is apparently typically lower in frequency than the bus clock. But&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;where does it come from and what's its value on these chips with fancy&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clock circuitry? Is it the same as the internal reference clock (~32kHz?)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Is it a divided version of the bus clock? The only docs for the source of&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;xclk was figure 1-2 in the datasheet, and i didn't find it helpful. All&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;other mentions of xclk describe how it is selected as an input for the&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;assorted timers and such.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Bill W&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 27 Jan 2007 10:53:27 GMT</pubDate>
    <dc:creator>billw</dc:creator>
    <dc:date>2007-01-27T10:53:27Z</dc:date>
    <item>
      <title>XCLK on QG4/8</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143727#M6678</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Ok, I read the datasheet, I looked at AN3041, and even some of the code&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;exmaples, but I'm still confused.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;XCLK is the "fixed frequency clock" selectable as inputs to the timers,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;and is apparently typically lower in frequency than the bus clock. But&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;where does it come from and what's its value on these chips with fancy&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clock circuitry? Is it the same as the internal reference clock (~32kHz?)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Is it a divided version of the bus clock? The only docs for the source of&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;xclk was figure 1-2 in the datasheet, and i didn't find it helpful. All&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;other mentions of xclk describe how it is selected as an input for the&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;assorted timers and such.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Bill W&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 27 Jan 2007 10:53:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143727#M6678</guid>
      <dc:creator>billw</dc:creator>
      <dc:date>2007-01-27T10:53:27Z</dc:date>
    </item>
    <item>
      <title>Re: XCLK on QG4/8</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143728#M6679</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Hello Bill,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;According to figure 1-2 in the datasheet, XCLK may be derived from either ICSFFCLK divided by 2, or alternatively from the bus clock, depending on the state of the ICSFFE control bit.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Then from figure 10-2, ICSFFCLK is derived from either the internal reference clock or an external reference, but will always be within the limits 31.25 to 39.0625 kHz.&amp;nbsp; Therefore, I would expect XCLK to be one half this frequency when ICSFFCLK is selected as the source.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Mac&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 27 Jan 2007 12:16:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143728#M6679</guid>
      <dc:creator>bigmac</dc:creator>
      <dc:date>2007-01-27T12:16:33Z</dc:date>
    </item>
    <item>
      <title>Re: XCLK on QG4/8</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143729#M6680</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Hello again,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;To slightly clarify my previous post, after some further reading -&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;The ICSFFE signal is automatically enabled provided the frequency of ICSOUT exceeds the frequency of ICSFFCLK by a factor of four, or greater (i.e. the bus frequency is at least four times the XCLK frequency).&amp;nbsp; The reason for this restriction is not clear to me.&amp;nbsp; Paragraph 10.4.7 of the datasheet explains the special conditions for which ICSFFE would be disabled.&amp;nbsp; But otherwise, what I stated in my previous post would seem to apply.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Mac&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 27 Jan 2007 14:37:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143729#M6680</guid>
      <dc:creator>bigmac</dc:creator>
      <dc:date>2007-01-27T14:37:59Z</dc:date>
    </item>
    <item>
      <title>Re: XCLK on QG4/8</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143730#M6681</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;So xclk will usually be irc/2 (~16kHz), unless the clock generator&lt;BR /&gt;is configured for particularly low frequencies, in which&lt;BR /&gt;case it would be the same as the bus clock.&lt;BR /&gt;&lt;BR /&gt;Ok, thanks.&lt;BR /&gt;BillW&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 28 Jan 2007 07:54:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/XCLK-on-QG4-8/m-p/143730#M6681</guid>
      <dc:creator>billw</dc:creator>
      <dc:date>2007-01-28T07:54:29Z</dc:date>
    </item>
  </channel>
</rss>

