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    <title>8-bit MicrocontrollersのトピックRe: Getting started with I2C on the QG8</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/Getting-started-with-I2C-on-the-QG8/m-p/143657#M6664</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Hi all,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I am now able to receive I2C data on the QG8, after some experimentation and code changes&lt;IMG alt=":smileyhappy:" class="emoticon emoticon-smileyhappy" id="smileyhappy" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-happy.gif" title="Smiley Happy" /&gt;&lt;/DIV&gt;&lt;DIV&gt;However, I have another question:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Using the following test code, the QG8 slave works great. I can receive 2 bytes in about 500 us, I am using a scope to measure this.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="msg_source_code"&gt;&lt;SPAN class="text_smallest"&gt;Code:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;PRE&gt; for(;;) {   __RESET_WATCHDOG(); /* feeds the dog */ if(IICS_TCF)   temp = IICD;   } &lt;/PRE&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;Now, if I add the .56 ms delay after reading the IICD Register, it seems that the QG8 is holding either the SCL or SDA line low for the entire delay time.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="msg_source_code"&gt;&lt;SPAN class="text_smallest"&gt;Code:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;PRE&gt; for(;;) {   __RESET_WATCHDOG(); /* feeds the dog */ if(IICS_TCF)   temp = IICD;  for (tmp=0; tmp&amp;lt;100; tmp++);     /* Delay (100 = .56ms delay)  */   } &lt;/PRE&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;I would expect that immediately after reading the TCF bit and the IICD register, the I2C Master would get the ACK bit and send the next byte. I have been going over the datasheet and any specs I can find, but I am stumped on this one. Even though the QG8 Slave is asserting the ACK bit, it seems like the I2C Bus is not "released" until the end of the for(;; ) loop.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Any thoughts on this one?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;TIA,&lt;BR /&gt;David&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="1"&gt;Alban: code format&lt;/FONT&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by Alban on &lt;SPAN class="date_text"&gt;2007-01-30&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;03:18 PM&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 29 Oct 2020 08:44:17 GMT</pubDate>
    <dc:creator>datamstr</dc:creator>
    <dc:date>2020-10-29T08:44:17Z</dc:date>
    <item>
      <title>Getting started with I2C on the QG8</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/Getting-started-with-I2C-on-the-QG8/m-p/143656#M6663</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Hi all,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I am using the QG8 and want to use the I2C Bus to receive data, first by polling.&amp;nbsp;I am sending I2C data from a Netburner Module (MOD-5270 Coldfire Processor). Question: What is the margin of error of the clock freq for the SCL to receive data on the QG8? The MCF5270 is transmitting at a clock freq of 64.102 KHZ. The signals look good on the scope. I have the QG8 setup to "receive" using the Device Initialization Bean in CW 5.0.&lt;/DIV&gt;&lt;DIV&gt;Also, the QG8 clock freq&amp;nbsp;is 62.5 KHZ in the CW Device Initialization GUI.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;MCUInit() Code:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Note: I am using PTB 6 and PTB7 for SDA and SCL.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;/* Common initialization of the write once registers */&lt;BR /&gt;&amp;nbsp;/* SOPT2: COPCLKS=0,IICPS=1,ACIC=0 */&lt;BR /&gt;&amp;nbsp;SOPT2 = 0x02;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;/* ### Init_IIC init code */&lt;BR /&gt;&amp;nbsp;/* IICA: ADDR6=0,ADDR5=0,ADDR4=0,ADDR3=0,ADDR2=0,ADDR1=0,ADDR0=1 */&lt;BR /&gt;&amp;nbsp;IICA = 0x02;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;/* IICF: MULT1=0,MULT0=1,ICR5=0,ICR4=0,ICR3=1,ICR2=0,ICR1=0,ICR0=1 */&lt;BR /&gt;&amp;nbsp;IICF = 0x49;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;/* IICC: IICEN=1,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0 */&lt;BR /&gt;&amp;nbsp;IICC = 0x80;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I am simply monitoring the incoming I2C data with:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;if(IICS_TCF)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;LED.Data[0][6] = IICD;&amp;nbsp; // turn on some LEDs on target board using SPI&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I suspect that the TCF flag is never getting set.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;What am&amp;nbsp;I missing for this to work?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks,&lt;BR /&gt;David&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Jan 2007 02:13:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/Getting-started-with-I2C-on-the-QG8/m-p/143656#M6663</guid>
      <dc:creator>datamstr</dc:creator>
      <dc:date>2007-01-26T02:13:01Z</dc:date>
    </item>
    <item>
      <title>Re: Getting started with I2C on the QG8</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/Getting-started-with-I2C-on-the-QG8/m-p/143657#M6664</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Hi all,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I am now able to receive I2C data on the QG8, after some experimentation and code changes&lt;IMG alt=":smileyhappy:" class="emoticon emoticon-smileyhappy" id="smileyhappy" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-happy.gif" title="Smiley Happy" /&gt;&lt;/DIV&gt;&lt;DIV&gt;However, I have another question:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Using the following test code, the QG8 slave works great. I can receive 2 bytes in about 500 us, I am using a scope to measure this.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="msg_source_code"&gt;&lt;SPAN class="text_smallest"&gt;Code:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;PRE&gt; for(;;) {   __RESET_WATCHDOG(); /* feeds the dog */ if(IICS_TCF)   temp = IICD;   } &lt;/PRE&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;Now, if I add the .56 ms delay after reading the IICD Register, it seems that the QG8 is holding either the SCL or SDA line low for the entire delay time.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="msg_source_code"&gt;&lt;SPAN class="text_smallest"&gt;Code:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;PRE&gt; for(;;) {   __RESET_WATCHDOG(); /* feeds the dog */ if(IICS_TCF)   temp = IICD;  for (tmp=0; tmp&amp;lt;100; tmp++);     /* Delay (100 = .56ms delay)  */   } &lt;/PRE&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;I would expect that immediately after reading the TCF bit and the IICD register, the I2C Master would get the ACK bit and send the next byte. I have been going over the datasheet and any specs I can find, but I am stumped on this one. Even though the QG8 Slave is asserting the ACK bit, it seems like the I2C Bus is not "released" until the end of the for(;; ) loop.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Any thoughts on this one?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;TIA,&lt;BR /&gt;David&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="1"&gt;Alban: code format&lt;/FONT&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;Message Edited by Alban on &lt;SPAN class="date_text"&gt;2007-01-30&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;03:18 PM&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Oct 2020 08:44:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/Getting-started-with-I2C-on-the-QG8/m-p/143657#M6664</guid>
      <dc:creator>datamstr</dc:creator>
      <dc:date>2020-10-29T08:44:17Z</dc:date>
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