SPI MC68HC908GP32

eli — Wed, 01 Aug 2007 05:28:21 GMT

I have 2 gp32's on a board, one a master SPI and one a slave SPI. Are there any examples for software (firmware) implementing a synchronous SPI link.

Added p/n to subject.

Message Edited by NLFSJ on 2007-07-31 06:53 PM

Re: SPI MC68HC908GP32

baddad — Thu, 02 Aug 2007 20:01:09 GMT

Here is an example of how I did the master end of things while connected to a SPI flash device.

The set up of the SPI was done using Procesor Expert.

Although this was using an S08 device, it should be very similar.

Hope it helps.

BadDad

Re: SPI MC68HC908GP32

rocco — Fri, 03 Aug 2007 05:18:10 GMT

Hi Eli,

Are you looking for assembly language code or C code?

Re: SPI MC68HC908GP32

bigmac — Fri, 03 Aug 2007 11:50:29 GMT

Hello,

To provide a SPI link, the actions required by the master will generally be dictated by the requirements of the slave device. In your case there is a little more flexibility, since the slave is a MCU. The following general issues will need to be considered to devise the link protocol. These are the ones that immediately come to mind - there are probably others.

Does the master need to interrogate different sorts of data from the slave, or does the slave return only one type of data?
If the data may consist of a variable number of bytes, how does the master know when the slave has reached the end of its current return data?
Since the slave cannot initiate a SPI transmission, how does the master know when the slave has data ready for sending?
After receipt of each byte from the master, how much time is required for the slave device to prepare the next data byte to be returned? This time will include the processing of any interrupts that may conceivably occur.

One possibility for solving some of these issues is for the slave device to provide an additional control signal back to the master. (This is in addition to the SS signal from master to slave.) This handshake signal would let the slave notify the master that it has data to send, and could also be used to indicate when each return byte was ready.

In all probability, the SPI master would not utilize SPI interrupt, whereas it is most likely the slave will require use of this interrupt in most instances.

Yet another possibility is to use a multi-master arrangement. Both ends of the link would remain in slave mode until there was data to be transferred. The originating end would then switch to master mode during the transfer.

The best solution will depend mostly on the nature of the data you require to transfer.

Regards,

Mac

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