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    <title>topic Re: SCI problem in 8-bit Microcontrollers</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139560#M5376</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Here is a quick go at a buffer based background transmit. Notice that the code never waits around doing nothing while the transmission occurs. Also if you are sending from many places in your code the buffer load bit is minimal.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;TXBUF       rmb    8              ;transmit bufferTXSTAT      rmb    1              ;transmit status bitsTXCHK       rmb    1              ;checksumTXCNT       rmb    1              ;transmit buffer index*somewhere in your code...            mov    #$3C,TXBUF            mov    #$07,TXBUF+1            mov    #$07,TXBUF+2            mov    #$07,TXBUF+3            mov    #$07,TXBUF+4            mov    #$00,TXBUF+5     ;mark end of string            bset   0,TXSTAT         ;mark to send            STARTMAIN   BLAH,BLAH            BLAHTXNEED      BRCLR  0,TXSTAT,MAINEND     ;bail if don't need to transmit            BRCLR  TDRE,SCI2S1,MAINEND  ;bail if Tx reg not MT            BRSET  1,TXSTAT,SENTADR     ;check if address sent            BSET   1,TXSTAT            BSET   RS485EN2,PTCD        ;enable transmitter            MOV    CARDADR,SCI2D        ;send address            BRA    CHK1SENTADR     BRSET  2,TXSTAT,SCITC       ;check if TXCHK sent            LDX    TXCNT                ;GET TX'D CHAR COUNT            INC    TXCNT            LDA    TXBUF,X              ;GET NEXT CHAR FROM TX1BUF            BEQ    CHKSM            STA    SCI2D                ;SEND CHAR            ADD    TXCHKCHK1        STA    TXCHK            BRA    MAINEND              ;KEEP GOING IF NOT ENDCHKSM       LDA    TXCHK            AND    #$7F            STA    SCI2D                ;SEND TXCHK            BSET   2,TXSTAT             ;set TXCHK sent            BRA    MAINENDSCITC       BRCLR  TC,SCI2S1,MAINEND    ;WAIT FOR TRANSMISSION COMPLETE            CLR    TXSTAT               ;clear status bits            BCLR   RS485EN2,PTCD        ;disable transmitter (enable recieve)            CLR    TXCNT                ;RESET TX COUNTERMAINEND     JMP    STARTMAIN&lt;/PRE&gt;&lt;/DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;Of course you may need some other code&amp;nbsp;to mark the end of the string, or, if you can't afford one use a "number of bytes to send" variable.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Did you get your comms to work?&lt;/DIV&gt;&lt;DIV&gt;I would not substitute this in until you get it working.&lt;/DIV&gt;&lt;DIV&gt;This is not going to fix any problems there.&lt;/DIV&gt;&lt;DIV&gt;Your original method is more basic and so a bit easier to debug.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 12 Jul 2007 06:11:31 GMT</pubDate>
    <dc:creator>peg</dc:creator>
    <dc:date>2007-07-12T06:11:31Z</dc:date>
    <item>
      <title>SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139553#M5369</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Hi, i wrote my code as below; but somehow when i single step thru i can't see my the data i sending out loaded in the data register.&lt;/DIV&gt;&lt;DIV&gt;I' using the SCI to drive a sipex SP485.&lt;/DIV&gt;&lt;DIV&gt;I inititalise the SCI as ;&lt;/DIV&gt;&lt;DIV&gt;4807baud&lt;/DIV&gt;&lt;DIV&gt;SCI2BDH = $00&lt;/DIV&gt;&lt;DIV&gt;SCI2BDL = $1A&lt;/DIV&gt;&lt;DIV&gt;SCI2C1&amp;nbsp;&amp;nbsp;&amp;nbsp; = $40&lt;/DIV&gt;&lt;DIV&gt;SCI2C1&amp;nbsp;&amp;nbsp;&amp;nbsp; = $2C&lt;/DIV&gt;&lt;DIV&gt;SCI2C3&amp;nbsp;&amp;nbsp;&amp;nbsp; = $00&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;;--------------------;TX485 Routine;--------------------tx485&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; bset&amp;nbsp;&amp;nbsp; RS485EN2,PTCD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; bset&amp;nbsp;&amp;nbsp; SCI2C2_TE,SCI2C2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; idelay&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; idelay&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; clr&amp;nbsp;&amp;nbsp;&amp;nbsp; TXCHK&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; TXADRtx485a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; brclr&amp;nbsp; SCI2S1_TDRE,SCI2S1,tx485a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; sta&amp;nbsp;&amp;nbsp;&amp;nbsp; SCI2D&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; add&amp;nbsp;&amp;nbsp;&amp;nbsp; TXCHK&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; sta&amp;nbsp;&amp;nbsp;&amp;nbsp; TXCHK&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; rts&amp;nbsp; ;--------------------;TX Data;--------------------txdata&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; CARDADR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; sta&amp;nbsp;&amp;nbsp;&amp;nbsp; TXADR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; tx485&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; #$3C&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; tx485a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; #$07&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; tx485a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; #$07&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; tx485a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; #$07&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; tx485a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; #$07&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; tx485a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; lda&amp;nbsp;&amp;nbsp;&amp;nbsp; TXCHK&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; and&amp;nbsp;&amp;nbsp;&amp;nbsp; #$7F&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; tx485atxdata2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; brclr&amp;nbsp; SCI2S1_TC,SCI2S1,txdata2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; jsr&amp;nbsp;&amp;nbsp;&amp;nbsp; idelayh&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; bclr&amp;nbsp;&amp;nbsp; RS485EN2,PTCD&lt;/PRE&gt;&lt;/DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;When i try to read SCI2D, it doesnt tally with the data i loaded.&lt;/DIV&gt;&lt;DIV&gt;Are there something wrong at my 'tx485a'?&lt;/DIV&gt;&lt;DIV&gt;Please advise.&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Message Edited by mingyee on &lt;/SPAN&gt;&lt;SPAN class="date_text"&gt;2007-07-09&lt;/SPAN&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;SPAN class="time_text"&gt;06:17 PM&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Jul 2007 00:16:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139553#M5369</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-10T00:16:02Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139554#M5370</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Hello,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Yes, it is correct that you won't read the byte you just sent&amp;nbsp;to SCI2D.&amp;nbsp; This is because the read of this register returns the last byte received by the SCI2 module, not the send byte.&amp;nbsp; For RS485 it is usual that, when send is enabled for the transceiver, receive will be disabled, so there would be no receive data.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Do you actually receive the sent data at the remote end?&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Mac&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Jul 2007 03:41:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139554#M5370</guid>
      <dc:creator>bigmac</dc:creator>
      <dc:date>2007-07-10T03:41:04Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139555#M5371</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;Your code looks OK, except that you appear to have a typo above the code box (second C1 should be C2). Baud OK assuming 2MHz buss.&lt;/DIV&gt;&lt;DIV&gt;So it is as Mac says if you have done the usual thing in hardware and tied TE and /RE together and controlled them with your RS485EN2. Only if you have permanently enabled the RE would you see what you have sent in the SCID.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Some notes on your code:&lt;/DIV&gt;&lt;DIV&gt;You initialise with TE then enable it again near tx485, unless your disabling for low power, just leave it on.&lt;/DIV&gt;&lt;DIV&gt;I have not found it necessary to delay between enabling TE and sending as in your double idelay.&lt;/DIV&gt;&lt;DIV&gt;Same goes for the other end with the single idelay.&lt;/DIV&gt;&lt;DIV&gt;Your code could perhaps benefit from loading the message into a buffer and having a routine that sends the buffer.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Jul 2007 06:16:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139555#M5371</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-10T06:16:18Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139556#M5372</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi bigmac, Thanks for the response.&lt;/DIV&gt;&lt;DIV&gt;From my understanding, when we sending data out we will move the data&amp;nbsp;to SCIxD.&lt;/DIV&gt;&lt;DIV&gt;Does that mean when i read SCIxD right after&lt;/DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;    sta   SCI2D&lt;/PRE&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;BR /&gt;&amp;nbsp;I will be able to see what i write into SCIxD?&lt;/DIV&gt;&lt;DIV&gt;At the other receiving end which is my laptop, I only receive 0 0 0 0 0 0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;IMG src="http://i20.photobucket.com/albums/b201/mingyee83/SCI2D.jpg" /&gt;&lt;BR /&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Please advise.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;PEG is right that I have typo (second C1 should be C2) at the initialize portion.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Jul 2007 11:14:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139556#M5372</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-10T11:14:21Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139557#M5373</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi PEG,&lt;/DIV&gt;&lt;DIV&gt;From your comment&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV&gt;&lt;HR /&gt;peg wrote:&lt;BR /&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Your code could perhaps benefit from loading the message into a buffer and having a routine that sends the buffer.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;BR /&gt;&lt;HR /&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV&gt;Any suggestion or recommendation doing it?&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Jul 2007 11:19:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139557#M5373</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-10T11:19:25Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139558#M5374</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;The SCID is actually two hardware registers located at the same address.&lt;/DIV&gt;&lt;DIV&gt;If you read that address you get the recieve buffer, if you write to it, you write into the transmit buffer.&lt;/DIV&gt;&lt;DIV&gt;It is impossible to read from the transmit buffer&amp;nbsp;or write to the recieve buffer!&lt;/DIV&gt;&lt;DIV&gt;This is spoken about in the SCI section of the manual.&lt;/DIV&gt;&lt;DIV&gt;The best way to use buffers is a bit protocol specific so I did not go into more detail straight away. If you tell me how it works maybe I can assist you implement it using buffers.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Jul 2007 14:34:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139558#M5374</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-10T14:34:16Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139559#M5375</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi Peg,&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;To store the data into a buffer I'll have to declare a buffer &amp;amp; use the stack pointer to move the data 1 by 1 into the buffer. Am i right?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;regards,&lt;/DIV&gt;&lt;DIV&gt;mingyee&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Jul 2007 21:10:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139559#M5375</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-11T21:10:01Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139560#M5376</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Here is a quick go at a buffer based background transmit. Notice that the code never waits around doing nothing while the transmission occurs. Also if you are sending from many places in your code the buffer load bit is minimal.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;TXBUF       rmb    8              ;transmit bufferTXSTAT      rmb    1              ;transmit status bitsTXCHK       rmb    1              ;checksumTXCNT       rmb    1              ;transmit buffer index*somewhere in your code...            mov    #$3C,TXBUF            mov    #$07,TXBUF+1            mov    #$07,TXBUF+2            mov    #$07,TXBUF+3            mov    #$07,TXBUF+4            mov    #$00,TXBUF+5     ;mark end of string            bset   0,TXSTAT         ;mark to send            STARTMAIN   BLAH,BLAH            BLAHTXNEED      BRCLR  0,TXSTAT,MAINEND     ;bail if don't need to transmit            BRCLR  TDRE,SCI2S1,MAINEND  ;bail if Tx reg not MT            BRSET  1,TXSTAT,SENTADR     ;check if address sent            BSET   1,TXSTAT            BSET   RS485EN2,PTCD        ;enable transmitter            MOV    CARDADR,SCI2D        ;send address            BRA    CHK1SENTADR     BRSET  2,TXSTAT,SCITC       ;check if TXCHK sent            LDX    TXCNT                ;GET TX'D CHAR COUNT            INC    TXCNT            LDA    TXBUF,X              ;GET NEXT CHAR FROM TX1BUF            BEQ    CHKSM            STA    SCI2D                ;SEND CHAR            ADD    TXCHKCHK1        STA    TXCHK            BRA    MAINEND              ;KEEP GOING IF NOT ENDCHKSM       LDA    TXCHK            AND    #$7F            STA    SCI2D                ;SEND TXCHK            BSET   2,TXSTAT             ;set TXCHK sent            BRA    MAINENDSCITC       BRCLR  TC,SCI2S1,MAINEND    ;WAIT FOR TRANSMISSION COMPLETE            CLR    TXSTAT               ;clear status bits            BCLR   RS485EN2,PTCD        ;disable transmitter (enable recieve)            CLR    TXCNT                ;RESET TX COUNTERMAINEND     JMP    STARTMAIN&lt;/PRE&gt;&lt;/DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;Of course you may need some other code&amp;nbsp;to mark the end of the string, or, if you can't afford one use a "number of bytes to send" variable.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Did you get your comms to work?&lt;/DIV&gt;&lt;DIV&gt;I would not substitute this in until you get it working.&lt;/DIV&gt;&lt;DIV&gt;This is not going to fix any problems there.&lt;/DIV&gt;&lt;DIV&gt;Your original method is more basic and so a bit easier to debug.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Jul 2007 06:11:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139560#M5376</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-12T06:11:31Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139561#M5377</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi Peg,&lt;/DIV&gt;&lt;DIV&gt;The old routine is working now.&lt;/DIV&gt;&lt;DIV&gt;I will be trying out your methods. It sounds more effecient compare to mine.&lt;/DIV&gt;&lt;DIV&gt;However, am i able to do the same for my RECEIVING?&lt;/DIV&gt;&lt;DIV&gt;Anything which I've to aware of?&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;mingyee&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Jul 2007 08:25:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139561#M5377</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-12T08:25:42Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139562#M5378</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi again mingyee,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I normally use something very similar to that shown for transmit although I normally use a unique header character which would then add another stage (and flag) to the transmit routine. You continually check for the header char and reset the index if you get one. This recovers from dropped/mangled chars faster.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;For recieve I always use an ISR and put it in a buffer checking for header and "my address" in the isr. Roughly the same technique is used but in reverse.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Why don't you give it a go yourself&amp;nbsp;and post it back here for perusal.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Jul 2007 09:00:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139562#M5378</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-12T09:00:19Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139563#M5379</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Hello mingyee,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;From your initial post, I might surmise that you are trying to implement a security card entry arrangement, and that you are using the RS485 link for a "master" controller to communicate with multiple card reader units, the "slaves".&amp;nbsp; Is this assumption&amp;nbsp;correct?&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;If so, I am unsure whether you are trying to implement the master end, the slave end, or both ends.&amp;nbsp; The approach to data buffering, and the use of interrupts, may differ somewhat depending of whether master or slave.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Does the master require to "poll" each slave in order to retrieve data from the particular slave, or is some other arrangement used?&amp;nbsp; After a slave sends data to the master, does the master then require to acknowledge the correct receipt, i.e. whether or not there is a&amp;nbsp;checksum error?&amp;nbsp; If an error is detected, what course of action does the slave take?&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;It is difficult to make further useful&amp;nbsp;suggestions without knowledge of the type of &amp;nbsp;communications protocol required.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Mac&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Jul 2007 17:58:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139563#M5379</guid>
      <dc:creator>bigmac</dc:creator>
      <dc:date>2007-07-12T17:58:26Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139564#M5380</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi Peg,&lt;/P&gt;&lt;P&gt;I've tried my buffering rx routine as follow.&lt;/P&gt;&lt;P&gt;it seems to work.&lt;/P&gt;&lt;P&gt;Any comment to make it more efficient?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;Code:;--------------------;RX485 rxirq routine;--------------------XDEF    isrVsci2rxisrVsci2rx:        pshh        clr     RXCHK        jsr     rx485        sta     RXDEV        bne     rxirq        jmp     rxirqz          rxirq   lda     RXDEV        cmp     #DEVICE         beq     rxirq1        jmp     rxirqzrxirq1  jsr     rx485        sta     RXADR        cmp     CARDADR        beq     rxirq2        jmp     rxirqzrxirq2  jsr     rx485        sta     RXCMD         rx0     cmp     #$55          ;poll status        bne     rx1        jmp     rxpoll     rx1                                 rxirqy  bclr    LBUSYF,SR2  rxirqz  pulh        rti;--------------------;RX485 Routine;--------------------rx485       clr    RXCTR            clr    RXLEN            mov    #$04,RXDEL            bset   LBUSYF,SR2rx485a      lda    #$00            feed_watchdog            ldx    RXLEN            brset  SCI2S1_RDRF,SCI2S1,rx485b              dec    RXCTR            bne    rx485a            dec    RXDEL            bne    rx485a                        rx485b      lda    SCI2D            sta    RXDATA            sta    RXBUF,X            add    RXCHK            sta    RXCHK            lda    RXDATA            inc    RXLENrx485z      rts       &lt;/PRE&gt;&lt;/DIV&gt;&lt;P&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;Regards,&lt;/P&gt;&lt;P&gt;mingyee&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 14 Jul 2007 11:28:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139564#M5380</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-14T11:28:17Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139565#M5381</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi Bigmac,&lt;/DIV&gt;&lt;DIV&gt;My application is quite similiar as u mentioned.&lt;/DIV&gt;&lt;DIV&gt;I believe buffering my tx reoutine is only applicable to my master to poll for slave.&lt;/DIV&gt;&lt;DIV&gt;Because my slave only feedback their status when everthey are polled.&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;regards,&lt;/DIV&gt;&lt;DIV&gt;mingyee&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 14 Jul 2007 11:33:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139565#M5381</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-14T11:33:35Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139566#M5382</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;You seem to have failed to grasp the basic concept of using an interrupt to do this.&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;Firstly without worrying too much about what the code is achieving, let me point out a few&lt;/DIV&gt;&lt;DIV&gt;inefficiencies in how you are going about it.&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;We will call the pshh at the top line 1.&lt;/DIV&gt;&lt;DIV&gt;1. At line 5,6 you are handling this as if a jmp is required. This can be handled directly by a branch and so both lines should be replaced by beq&amp;nbsp; rxirqz.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;2. Line 7, you are loading the accumulator with a value that it already has, drop this line.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;3. Line 9,10 and 14,15 and 19,20 same as point 1.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;4. where is rxpoll?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;5. at rx485a, probably no need to clra before feed_watchdog.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;6. You should not feed the watchdog from within an isr!&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;7. Doing a jsr out of an ISR is usually not a good idea it should be simple enough to not require this much overhead.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;That will do for that.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Now, the idea of an SCI recieve ISR is simply this. Every time a character comes in the ISR fires then within the isr you simply get the char, do a quick analysis of it and set a bit or store it in a buffer then get out back to background tasks waiting for the next character to trundle in.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;If you want to do a time out, do it in the background.&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;In the ISR you set a bit or something to indicate that you have the entire message and then further processing is done by code in the background.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;If you tell me what you are expecting to recieve maybe I can help with a routine.&lt;BR /&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 15 Jul 2007 08:35:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139566#M5382</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-15T08:35:38Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139567#M5383</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Hi Peg,&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;My rxpoll routine is as below.&lt;/DIV&gt;&lt;DIV&gt;After checking what the RXCMD is then I'll jmp to respective RXPOLL for its dedicated action.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;rxpoll  jsr     rxchksum  ;chksum        bne     rxirqzrxpoll1 lda     CARDADR   ;slave adr for master to identify        sta     TXADR         jsr     tx485        lda     #$3C      ;command        jsr     tx485a        lda     #$07      ;txdta        jsr     tx485a        lda     #$07      ;txdta1        jsr     tx485a        lda     #$07      ;txdta2        jsr     tx485a        lda     #$07      ;txdta3        jsr     tx485a        lda     TXCHK     ;txchksum        and     #$7F        jsr     tx485a          rxpoll2 brclr   SCI2S1_TC,SCI2S1,rxpoll2        jsr     idelayh        bclr    RS485EN2,PTCD                         pulh        rti&lt;/PRE&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;what I'm expecting to receive is&lt;/DIV&gt;&lt;DIV&gt;1. "RXDEV, RXADR, RXCMD,RXDTA(1-n),&amp;nbsp;RXCHK" for MASTER to SLAVE&lt;/DIV&gt;&lt;DIV&gt;2. "RXADR, RXCMD,RXDTA(1-n),&amp;nbsp;RXCHK" for SLAVE to MASTER&lt;/DIV&gt;&lt;DIV&gt;RXDEV&amp;nbsp;=&amp;nbsp;different for different slave system or device&lt;/DIV&gt;&lt;DIV&gt;RXADR = for MASTER to SLAVE reflects to slave adr / for SLAVE to MASTER reflects to slave adr itself for master to identify&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;RXCMD = command&lt;/DIV&gt;&lt;DIV&gt;RXDTA = data for each command&lt;/DIV&gt;&lt;DIV&gt;RXCHK = chksum by adding all the bytes in front&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I would like to chk if it is possible to do something like:&lt;/DIV&gt;&lt;DIV&gt;1. i chk for the RXDEV if valid then i buffer everything into RXBUF&lt;/DIV&gt;&lt;DIV&gt;2. then chk&amp;nbsp;RXADR if valid&lt;/DIV&gt;&lt;DIV&gt;3.&amp;nbsp;then chk RXCHK if valid&lt;/DIV&gt;&lt;DIV&gt;4. then&amp;nbsp;cmp command &amp;amp; process the data?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I see that what I'm currently doing is while i receive i chk &amp;amp; compare the data receive.&lt;/DIV&gt;&lt;DIV&gt;Please advise.&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;mingyee&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;Message Edited by mingyee on &lt;SPAN class="date_text"&gt;2007-07-15&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;05:21 AM&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 15 Jul 2007 11:03:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139567#M5383</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-15T11:03:49Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139568#M5384</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I am still unclear on a couple of things to do with the protocol, like:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;How do you identify the start of a new transmission?&lt;BR /&gt;What do you do if, say, the checksum is wrong?&lt;BR /&gt;What is a valid RXDEV?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;What I will do is give you my version of a rx ISR for the slave in psuedo code&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;load SCI status reg&lt;BR /&gt;check for errors and ???&lt;BR /&gt;load SCI data reg&lt;/DIV&gt;&lt;DIV&gt;if have not got valid RXDEV&lt;BR /&gt;&amp;nbsp; check for valid RXDEV&lt;BR /&gt;&amp;nbsp; if OK reset buffer index&lt;BR /&gt;&amp;nbsp; store it in RXCHKS&lt;BR /&gt;&amp;nbsp; and set gat valid RXDEV&lt;/DIV&gt;&lt;DIV&gt;if got valid rxdev but not my address bit&lt;BR /&gt;&amp;nbsp; check for my address&lt;BR /&gt;&amp;nbsp; if not, clear got valid RXDEV&lt;BR /&gt;&amp;nbsp; if is mw address set bit to say so&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; add to RXCHKS&lt;/DIV&gt;&lt;DIV&gt;if got valid rxdev and my address&lt;BR /&gt;&amp;nbsp; buffer the rest&lt;BR /&gt;&amp;nbsp; add to RXCHKS&lt;BR /&gt;&amp;nbsp; if this is RXCHK&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; cmp to calculated RXCHKS&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; if OK set bit to say got a valid string and clear all other bits&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;......&lt;/DIV&gt;&lt;DIV&gt;in your background code now you can detect the "got valid string bit"&lt;BR /&gt;now you can intepret it.&lt;BR /&gt;In the buffer is only the command and its data.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 15 Jul 2007 15:26:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139568#M5384</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-15T15:26:13Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139569#M5385</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Hello mingyee,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;To elaborate on Peg's comments about your protocol . . .&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;For a slave to identify whether the value of RXDEV is valid, it first of all needs to identify which incoming byte represents RXDEV.&amp;nbsp; Bear in mind that, for a RS485 system,&amp;nbsp;each slave will receive the transmissions from every other slave, as well as the master.&amp;nbsp; Therefore,&amp;nbsp;the value of RXDEV itself must be unique, and must never appear elsewhere within any data packet.&amp;nbsp; Alternatively, the value of RXDEV must be preceeded by a single character,&amp;nbsp;or sequence of characters, that will identify the start of a packet, and again this must not appear elswhere within a packet.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;If the data within a packet&amp;nbsp;consists of&amp;nbsp;binary data that may have any value, one approach is for the SCI to use 9-bit data mode.&amp;nbsp; The start of a packet, and the value of RXDEV, can then be identified by the 9th bit being set for this character, and clear for all other characters.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;If the data can be restricted to ASCII characters (7-bit), the normal 8-bit data mode could be used, and RXDEV identified with the eighth bit set.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;If the data is further restricted to&amp;nbsp;printable ASCII characters, it should be possible to use a control character to represent the start of a packet.&amp;nbsp; Of course, the checksum byte value would also need to be represented by two ASCII characters (non-control).&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Another related issue, is to identify when the end of a packet is reached, especially if the length of a packet may vary.&amp;nbsp;&amp;nbsp;One choice would be to allocate a byte, perhaps immediately following RXDEV,&amp;nbsp;to represent the length of the packet.&amp;nbsp; Alternatively, a&amp;nbsp;control character to represent the end of the packet might be used.&amp;nbsp; The checksum byte(s)&amp;nbsp;could follow this character.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;When the master receives a response from the slave, and a checksum error is detected, in many cases the master should request that the slave resend&amp;nbsp;its previous&amp;nbsp;packet.&amp;nbsp; One method I have used is for the master to respond to the received packet&amp;nbsp;by sending&amp;nbsp;an ACK control character if OK, and a NAK character if a resend is required.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Regards,&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT size="2"&gt;Mac&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Jul 2007 01:44:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139569#M5385</guid>
      <dc:creator>bigmac</dc:creator>
      <dc:date>2007-07-16T01:44:35Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139570#M5386</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Mac's comments have now prompted me to ask you:&lt;/DIV&gt;&lt;DIV&gt;Are you making up this protocol yourself or are you following some pre-defined protocol?&lt;/DIV&gt;&lt;DIV&gt;I had thought you were following an already defined one and is why I have been asking rather than suggesting/telling.&lt;/DIV&gt;&lt;DIV&gt;This was actually reinforced by Mac's comment that it was for some kind of sercurity/entry system although I am not sure how he came to that conclusion. (I presumed he recognised the byte sequence?)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Of course if you are making this protocol up for yourself then further consideration taking Mac's comments in would be advised. One point I would like to add is that not all ASCII protocols send the checksum as ASCII. Simple XOR types often send it as binary or like you have done earlier simply lop off the MSB.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;Message Edited by peg on &lt;SPAN class="date_text"&gt;2007-07-16&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;09:09 AM&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Jul 2007 05:40:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139570#M5386</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-16T05:40:45Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139571#M5387</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Thanks Peg &amp;amp; Mac,&lt;/DIV&gt;&lt;DIV&gt;I'm actually experimenting some audio control system adopting the distributed architecture of an security system. I'd say I'm seeking your advise to find out&amp;nbsp;how to&amp;nbsp;produce&amp;nbsp;an efficient protocol.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I'll explain further my thoughts for the protocol I'm using currently.&lt;/DIV&gt;&lt;DIV&gt;Where there is an chksum error,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;1. from master&amp;nbsp;to slave&lt;/DIV&gt;&lt;DIV&gt;- slave will ignore &amp;amp; wait to be poll again&lt;/DIV&gt;&lt;DIV&gt;- when an command is received from master to slave, slave will reply with an ack command with its slave address in it.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;2. from slave to master&lt;/DIV&gt;&lt;DIV&gt;-master will resend msg again up to 3 times b4 concluding the particular slave failed &amp;amp; will indicate error to user.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;basically the slave only listen &amp;amp; respond to master.&lt;/DIV&gt;&lt;DIV&gt;This is not a critical system, so I wanted to make the protocol a simple one.&lt;/DIV&gt;&lt;DIV&gt;Yes i did notice about the ASCII part that's why I mask off&amp;nbsp; the MSB.&lt;/DIV&gt;&lt;DIV&gt;The RXDEV is unique &amp;amp; different master will have a different RXDEV. They are read from the dip-switch setting on the master.&lt;/DIV&gt;&lt;DIV&gt;Adding the length bytes is brilliant, I will add that portion in &amp;amp; will also be looking into both comments given by both of you &amp;amp; try to implement&amp;nbsp;them &amp;amp; post it up for your comments.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thank you very much.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Jul 2007 08:48:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139571#M5387</guid>
      <dc:creator>mylim</dc:creator>
      <dc:date>2007-07-16T08:48:57Z</dc:date>
    </item>
    <item>
      <title>Re: SCI problem</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139572#M5388</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi mingyee,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I think you would be best to adopt a fixed header character, say ASCII &amp;lt;STX&amp;gt;.&lt;/DIV&gt;&lt;DIV&gt;Then you need either of the following:&lt;/DIV&gt;&lt;DIV&gt;1. fixed length messages, shorter ones are padded, like leading zeroes&lt;/DIV&gt;&lt;DIV&gt;2. a termination character, say ASCII &amp;lt;ETX&amp;gt;&lt;/DIV&gt;&lt;DIV&gt;3. a length byte, probably straight behind the header.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;This not only improves the robustness of the protocol, but makes it easier to implement.&lt;/DIV&gt;&lt;DIV&gt;If the messages are very short fixed length can be best/more efficient.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Doing this also speeds recovery from a dropped or garbled byte. Generally without proper framing like this the following good message will be lost as well as it will be needed to re-sync. Having a header means every message re-syncs the comms.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;There are so many ways to do this that you will get a different answer from all you ask. However I believe this is the minimum for a simple protocol.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;header, address, command, data, checksum, terminator.&lt;/DIV&gt;&lt;DIV&gt;or&lt;/DIV&gt;&lt;DIV&gt;header, length, address, command, data, checksum.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Is this system single master?&lt;/DIV&gt;&lt;DIV&gt;If single will it have an address like a slave, say 0, or will the format be different for master messages.&lt;/DIV&gt;&lt;DIV&gt;This affects how the response is structured, but possibly:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;header, master address, slave address, &amp;lt;ACK&amp;gt; or data, checksum, terminator&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;or&lt;/DIV&gt;&lt;DIV&gt;header, master address, slave address, length, &amp;lt;ACK&amp;gt; or data, checksum&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;your RXDEV could be added in front of the ack/data&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Multi-master has many other issues not addressed here.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Jul 2007 14:02:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/SCI-problem/m-p/139572#M5388</guid>
      <dc:creator>peg</dc:creator>
      <dc:date>2007-07-16T14:02:38Z</dc:date>
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