topic Re: TPM1 and TPM2 counters run at different rates in 8-bit Microcontrollers

TPM1 and TPM2 counters run at different rates

EtherJones — Thu, 23 Nov 2006 14:26:43 GMT

MC9S08DZ60.

TPM1 and TPM2 both set to bus rate clock, prescale=1.

TPM1MODH:L and TPM2MODH:L both set to the same values.

TPM1 and TPM2 both set to generate interrupts on overflow.

ISR's for each have a counter.

But the counters run at different rates ! I thought the counter values should be indentical. What am I missing here?

Re: TPM1 and TPM2 counters run at different rates

Pingu — Thu, 23 Nov 2006 19:35:01 GMT

Hi Esther,

This is all to do with the fact that you have two timers running almost in synchronise and the TPM1 interrupt vector has a higher priority than the TPM2. When both TOF flags are set TPM1 ISR is always executed first even if TPM2 was set first and while in an ISR all other interrupts are masked.

If you set a breakpoint in each ISR you will be able to see this happening. TPM1 ISR will be running while both timers continue in the background, TOF[2] is set. Before it exists TOF[1] is set again so the ISR[1] runs. This is how your counters are getting out of sync.

Hope this explanation makes sense :smileywink:

Pingu

Re: TPM1 and TPM2 counters run at different rates

bigmac — Thu, 23 Nov 2006 21:01:22 GMT

Hello Ester,

With Pingu's explanation, there should never be more than a difference of one between the two counter values. Is this what you observe? The count rate should be the same for both, however both counter values cannot simultaneously increment.

Note that the PWM output signals associated with each TPM module should remain synchronous within a few bus cycles, since these are determined by the timer hardware within the MCU.

It probably does not apply to your simple sample code, but there would need to be a further consideration for the more general case. Since you have set the timer modulo value to give an overflow period of 201 cycles for each module, this would require that the two timer overflow ISRs, plus any other ISR that may possibly occur, must all be able to execute in somewhat less than 201 cycles in total. Otherwise, this would lead to erratic operation of the software counters. In many instances, meeting this limit would not be possible.

Regards,

Mac

Re: TPM1 and TPM2 counters run at different rates

EtherJones — Fri, 24 Nov 2006 00:28:23 GMT

With Pingu's explanation, there should never be more than a difference of one between the two counter values. Is this what you observe?

No. The timers are running at different rates. The TPM1 timer is running 15% faster than TPM2. The ratio between the two timer counters is about 1.15 to 1. So the longer I let it run, the greater the numerical difference between the two counters.

What could cause this?

Re: TPM1 and TPM2 counters run at different rates

Geezer — Fri, 24 Nov 2006 00:37:26 GMT

As Mac said your TOTAL interrupt service time is most likely longer than the rate at which the interrupts are coming in, this is a no-no. Then Pingu's obsevation comes in... TIM1 does have priority, and if interrupt requests are stacked it will get more frequent attention.

Experiment a bit... increase your TIMx modulo values... by a lot more than 15%. :smileyhappy: The problems just may vanish.

Al