8-bit Microcontrollers中的主题 Re: CPU cycles vs. Instruction cycles vs. BUS cycles vs. Oscillator cycles

CPU cycles vs. Instruction cycles vs. BUS cycles vs. Oscillator cycles

Luigi — Thu, 19 Apr 2007 00:02:06 GMT

I am migrating from another micro to the HCS08AW32 processor and I wanted to be sure I know how the clocks work. From what I gather in the manual, if I have an external 4 MHz resonator, and my ICGC2 register is set to divide by 1, I think I have IGCOUT of 4 MHz, right? The block diagram shows that connecting directly to the CPU block, so can I assume that instructions are running with an instruction cycle time of 250 nS (i.e. 4 MHz)? Or is the 4 MHz divided down such that a CPU cycle is more than one oscillator cycle? My CodeWarrior debugger shows what I think is BUSCLK cycles which is IGCOUT/2 or 2 MHz. But it looks like BUSCLK is used by internal peripherals like the TPM, so I am not sure what the speed of a CPU cycle is. Can someone get me straight on this? Thanks

Re: CPU cycles vs. Instruction cycles vs. BUS cycles vs. Oscillator cycles

tonyp — Thu, 19 Apr 2007 00:15:41 GMT

All 9S08 MCUs have a final division by 2 to derive the bus clock. This of course is after any dividers or prescalers (e.g., RDIV, BDIV, etc) are applied. In other words, if all prescalers are set to divide by 1, the final bus clock will be exactly half the original clock (or FLL derived clock, ICSOUT, or ICGOUT). If you look at the block diagrams, there is always a /2 block right before the BUSCLK

With a 4MHz clock you can't get any higher than 2MHz bus.

Re: CPU cycles vs. Instruction cycles vs. BUS cycles vs. Oscillator cycles

Luigi — Thu, 19 Apr 2007 01:52:50 GMT

Yes, I can see that about BUSCLK. But I am wondering what speed the CPU instructions are running at. If an instruction takes 2 "cycles", what cycles are they talking about, oscillator cycles? The thing about CodeWarrior's debugger is it seems to indicate BUSCLK cycles. I just wonder how fast instructions actually run.

Re: CPU cycles vs. Instruction cycles vs. BUS cycles vs. Oscillator cycles

joerg — Thu, 19 Apr 2007 02:31:19 GMT

Ciao Luigi
In general the CPUs are running on the BUSCLK so a instruction using two cycles uses 2 BUSCLKs or in your case four osc cycles. I would do the calculations always based on BUSCLKs.

Saluti Joerg

Re: CPU cycles vs. Instruction cycles vs. BUS cycles vs. Oscillator cycles

Luigi — Thu, 19 Apr 2007 03:03:29 GMT

OK, that's what I thought, although the diagram shows the line going directly from the ICG to the CPU block, which made me think that the CPU block was operating on 4 MHz. I guess it might actually be, but it might operate internally such that it essentially divides by 2 as it executes instructions. Having done micro-code for a bit-slice micro before, I know how that works. Anyway, I appreciate your response.

Grazie!