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    <title>topic Re: HC908GP32 Timer question in 8-bit Microcontrollers</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1769872#M23818</link>
    <description>&lt;P&gt;After validating the code, I see some instructions that I would like to understand.&lt;/P&gt;
&lt;P&gt;I see that you enabe the interruption by using the command mov #%01000000,T1SC0, after more setup commands you disable the same interruption by using bclr CHxIE,T1SC0, which means that the interruption will only be active during that setup procedure, right?&lt;/P&gt;
&lt;P&gt;Also, I see that you are not using the CLI for general interruptions. Can you please try using it?&lt;/P&gt;</description>
    <pubDate>Wed, 06 Dec 2023 15:53:03 GMT</pubDate>
    <dc:creator>Itzzamna_Supp</dc:creator>
    <dc:date>2023-12-06T15:53:03Z</dc:date>
    <item>
      <title>HC908GP32 Timer question</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1766938#M23814</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;I'm using an HC908GP32 as an engine controller and have been stumped by what I thought should be an easy thing. I want to generate a single pulse width for fuel injector control using Tim1 CH0 for injector 1, and CH1 for injector 2. Below is the code I'm using to initialize Port D, the Tim1 timer, the calling code for inj1 and the CH0 interrupt service routine. For some reason I'm not getting an interrupt for either channel. Any help would be greatly appreciated. Here' my code:&lt;/P&gt;&lt;DIV&gt;; MC68HC908GP32 40 Pin&lt;/DIV&gt;&lt;DIV&gt;; PORT D INIT&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;; Port D&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$30,PORTD&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Move %00110000 to Port D Data Direction Register (preinit output&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; pins 5,4 Hi)(Turn off injectors (inverted output)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF,DDRD&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Move %11111111 to Port D Data Direction Register&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; (PTD7,6 not available, outputs on PTD5,4,3,2,1,0&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; = N/A,N/A,Inj1,Inj2,N/C,N/C,N/C,N/C&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;; TIM1 INIT&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;; Set up TIM1 as a free running ~1us counter. Set channels 0 and 1 for output&lt;/DIV&gt;&lt;DIV&gt;; compare, pulsewidth control of injectors. INJ1 on T1SC0 and INJ2 on T1SC1&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#%00110011,T1SC&amp;nbsp; ; Move %00110011 into Timer1 Status and Control Register&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 TOF, (no effect)&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 TOIE, (Overflow interrupts disabled)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 TSTOP, (counter stopped)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 TRST, (Prescale and counter cleared)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bits 2,3,0 (Prescale for bus frequency / &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF,T1MODH&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Move decimal 255 into T1 modulo reg Hi (Free running timer)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF,T1MODL&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Move decimal 255 into T1 modulo reg Lo&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; #%01000000,T1SC0 ; Channel 1 Output compare, interrupt enabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH0 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH0 interrupts enabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 MSxB, CH0 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 MSxA, CH0 Initial output level Hi (Inj1 off)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 ELSxB, CH0 Pin under port control&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 ELSxA, CH0 Pin under port control&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 TOVx, CH0 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 CHxMAX, CH0 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; #$00,T1CH0H&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Move decimal 0 to T1CH0 register Hi&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; #$00,T1CH0L&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Move decimal 0 to T1CH0 register Lo&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp;CHxF,T1SC0&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Clear CH0 output compare flag&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp;CHxIE,T1SC0&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Disable CH0 interrupt until we are ready&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; #%01000000,T1SC1 ; Channel 1 Output compare, interrupt enabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH1 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH1 interrupts enabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 MSxB, CH1 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 MSxA, CH1 Initial output level Hi (Inj2 off)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 ELSxB, Pin under port control&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 ELSxA, Pin under port control&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 TOVx, CH1 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 CHxMAX, CH0 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; #$00,T1CH1H&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Move decimal 0 to T1CH0 register Hi&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; #$00,T1CH1L&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Move decimal 0 to T1CH0 register Lo&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp;CHxF,T1SC1&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Clear CH1 output compare flag&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp;CHxIE,T1SC1&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Disable CH1 interrupt until we are ready&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; mov&amp;nbsp; &amp;nbsp; #%01010011,T1SC ; Start timer, no overflow int, div / 8&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 TOF, (no effect)&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 TOIE, (overflow interrupts enabled)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 TSTOP, (counter active)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 TRST, (Prescale and counter cleared)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bits 2,3,0 (Prescale for bus frequency / &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;****************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;; CALL FOR INJECTOR PULSE 1 IN PROGRAM&lt;/DIV&gt;&lt;DIV&gt;;****************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; lda&amp;nbsp; &amp;nbsp; &amp;nbsp;T1CNTL&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Unlatch any previous reads&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; lda&amp;nbsp; &amp;nbsp; &amp;nbsp;pwcalc1L&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; uS pulse width Lo byte&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; add&amp;nbsp; &amp;nbsp; &amp;nbsp;T1CNTL&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; A&amp;lt;-(A)+(M) Current counter value Lo byte&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; tax&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; (A)-&amp;gt;(X) Result to X&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; lda&amp;nbsp; &amp;nbsp; &amp;nbsp;pwcalc1H&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; uS pulse width Hi byte&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; adc&amp;nbsp; &amp;nbsp; &amp;nbsp;T1CNTH&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; A&amp;lt;-(A)+(M)+(C) Current counter value Hi byte&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; sta&amp;nbsp; &amp;nbsp; &amp;nbsp;T1CH0H&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Write high byte timer output compare first&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; stx&amp;nbsp; &amp;nbsp; &amp;nbsp;T1CH0L&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Then low byte&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp; inject1,portd&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Turn on Injector #1 (inverted drive)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp; CHxF,T1SC0 &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Clear CH0 output compare flag&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bset&amp;nbsp; &amp;nbsp; CHxIE,T1SC0&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Enable CH0 interrupt&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;****************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;; TIM1 CHANNEL 0 INTERRUPT SERVICE ROUTINE&lt;/DIV&gt;&lt;DIV&gt;;***************************************************************************&lt;/DIV&gt;&lt;DIV&gt;; - TIM1_CH0_ISR (Inj1 control)&lt;/DIV&gt;&lt;DIV&gt;;**************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;TIM1_CH0_ISR:&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; pshh&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; lda&amp;nbsp; &amp;nbsp; &amp;nbsp;T1SC0&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Read interrupt&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp; CHxF,T1SC0 &amp;nbsp; &amp;nbsp; &amp;nbsp;; Reset interrupt flag&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bclr&amp;nbsp; &amp;nbsp; CHxIE,T1SC0&amp;nbsp; &amp;nbsp; &amp;nbsp;; Disable interrupt&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; bset&amp;nbsp; &amp;nbsp; inject1,portd&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Turn Off Injector #1 (inverted drive)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; pulh&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; rti&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;***************************************************************************&lt;/DIV&gt;</description>
      <pubDate>Fri, 01 Dec 2023 05:44:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1766938#M23814</guid>
      <dc:creator>roberthiebert</dc:creator>
      <dc:date>2023-12-01T05:44:49Z</dc:date>
    </item>
    <item>
      <title>Re: HC908GP32 Timer question</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1769872#M23818</link>
      <description>&lt;P&gt;After validating the code, I see some instructions that I would like to understand.&lt;/P&gt;
&lt;P&gt;I see that you enabe the interruption by using the command mov #%01000000,T1SC0, after more setup commands you disable the same interruption by using bclr CHxIE,T1SC0, which means that the interruption will only be active during that setup procedure, right?&lt;/P&gt;
&lt;P&gt;Also, I see that you are not using the CLI for general interruptions. Can you please try using it?&lt;/P&gt;</description>
      <pubDate>Wed, 06 Dec 2023 15:53:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1769872#M23818</guid>
      <dc:creator>Itzzamna_Supp</dc:creator>
      <dc:date>2023-12-06T15:53:03Z</dc:date>
    </item>
    <item>
      <title>Re: HC908GP32 Timer question</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1770395#M23819</link>
      <description>&lt;P&gt;Hi Itzzamna,&lt;/P&gt;&lt;P&gt;So sorry about my late reply, I didn't get any e-mail notification.&lt;/P&gt;&lt;P&gt;In the set up procedure, after I have set things up, I disable the interrupt until I am ready to use it. I enable it again in the code at the time that I have the output compare values set and want to enable the interrupt. I think that's the correct way to do it.&lt;/P&gt;&lt;P&gt;I'm in the process of setting up a development board to test my code and should have it ready in a day or so. When it's up and running I will try your&amp;nbsp; suggestion and get back to you as soon as I can. Thanks for taking the time to reply.&lt;/P&gt;&lt;P&gt;Robert&lt;/P&gt;</description>
      <pubDate>Thu, 07 Dec 2023 04:25:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1770395#M23819</guid>
      <dc:creator>roberthiebert</dc:creator>
      <dc:date>2023-12-07T04:25:39Z</dc:date>
    </item>
    <item>
      <title>Re: HC908GP32 Timer question</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1771810#M23820</link>
      <description>&lt;P&gt;Well, I'm not doing too good with this. I set up another board just to experiment with coding just so I know that there would be nothing in my main code that would be there to cause issues. I think there is something wrong with the way I am setting up Tim1. Probably because I am not completely clear on how to do this for what I want it to do.&lt;/P&gt;&lt;P&gt;This is what I want it to do:&lt;/P&gt;&lt;P&gt;I have Port D4 set up as an output for Inj1. Port D5 is set up as an output for Inj2. Both are hardware inverted.&lt;/P&gt;&lt;P&gt;I have Tim1 set up as a free running counter. I have both Ch0 and Ch1 set up as output compare and the pins are under port control.&amp;nbsp; I want Ch0 to control Inj1 and Ch1 to control Inj2. In my program when I get an input signal that it is time to energize Inj1 for a particular pulse width, I will get a time stamp of the Tim1 counter, add the pulse width to it, save these values to the T1CH0H;T1CH0L registers, Clear the Inj1 pin on Port D to start the injection and and enable the interrupt. In the Tim1 Ch0 ISR I will disable the interrupt and set the Inj1 pin of Port D to terminate the injection. I'll use the same procedure for Inj2.&lt;/P&gt;&lt;P&gt;Here is how I have things set up:&lt;/P&gt;&lt;DIV&gt;;****************************************************************************&lt;/DIV&gt;&lt;DIV&gt;; - Set Port D for injector control (injectors hardware inverted), Input&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;&amp;nbsp; &amp;nbsp;status LED, and spark control&lt;/DIV&gt;&lt;DIV&gt;;****************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;; Port D&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$30,PORTD&amp;nbsp; &amp;nbsp; &amp;nbsp; ; %00110000 to port D Data register&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; (Inj2,Inj1 high, all others low&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;lda&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Load accumulator with %11111111&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; (port direction setup 1 = output)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;sta&amp;nbsp; &amp;nbsp; &amp;nbsp;DDRD&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Copy to Port D Data Direction Register&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; (Set all as outputs)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; NA,NA,Inj2,Inj1,Input Stat,SpkB,SpkA,NA)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;; Set up TIM1 as a free running ~1us counter. Set channels 0 and 1 for output&lt;/DIV&gt;&lt;DIV&gt;; compare, pulsewidth control of injectors. INJ1 on T1SC0 and INJ2 on T1SC1&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#%00110011,t1sc&amp;nbsp; ; Move %00110011 into Timer1 Status and Control Register&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 TOF, (no effect)&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit6 TOIE, (Overflow interrupts disabled)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit5 TSTOP, (counter stopped)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit4 TRST, (Prescale and counter cleared)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bits 2,1,0 (Prescale for bus frequency / &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF,t1modh&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Move decimal 255 into T1 modulo reg Hi (Free running timer)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF,t1modl&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Move decimal 255 into T1 modulo reg Lo&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #%11010000,t1sc0 ; Channel 1 Output compare, interrupt enabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH0 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH0 interrupts enabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 MSxB, CH0 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 MSxA, CH0 Unbuffered output compare/PWM operation&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 ELSxB, CH0 Pin under port control initial output high&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 ELSxA, CH0 Pin under port control initial output high&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 TOVx, CH0 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 CHxMAX, CH0 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #%11010000,t1sc1 ; Channel 1 Output compare, interrupt enabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH0 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH0 interrupts enabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 MSxB, CH0 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 MSxA, CH0 Unbuffered output compare/PWM operation&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 ELSxB, CH0 Pin under port control initial output high&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 ELSxA, CH0 Pin under port control initial output high&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 TOVx, CH0 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 CHxMAX, CH0 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; mov&amp;nbsp; &amp;nbsp; #%01010011,t1sc ; Start timer, no overflow int, div / 8&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 TOF, (no effect)&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 TOIE, (overflow interrupts enabled)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 TSTOP, (counter active)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 TRST, (Prescale and counter cleared)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bits 2,1,0 (Prescale for bus frequency / &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Is there anything wrong with the way I have Port B and the timer set up?&lt;/DIV&gt;&lt;DIV&gt;Any suggestions would be greatly appreciated&lt;/DIV&gt;&lt;DIV&gt;Robert&lt;/DIV&gt;</description>
      <pubDate>Sun, 10 Dec 2023 00:41:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1771810#M23820</guid>
      <dc:creator>roberthiebert</dc:creator>
      <dc:date>2023-12-10T00:41:08Z</dc:date>
    </item>
    <item>
      <title>Re: HC908GP32 Timer question</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1771832#M23821</link>
      <description>&lt;P&gt;Update:&lt;/P&gt;&lt;P&gt;&amp;nbsp;I've made some progress. I kept trying different combinations for the TIM1 set up and finally got the correct one. I don't know why it works, but it works. Here it is:&lt;/P&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;; Set up TIM1 as a free running ~1us counter. Set channels 0 and 1 for output&lt;/DIV&gt;&lt;DIV&gt;; compare, pulsewidth control of injectors. INJ1 on T1SC0 and INJ2 on T1SC1&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#%00110011,t1sc&amp;nbsp; ; Move %00110011 into Timer1 Status and Control Register&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 TOF, (no effect)&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 TOIE, (Overflow interrupts disabled)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 TSTOP, (counter stopped)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 TRST, (Prescale and counter cleared)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bits 2,1,0 (Prescale for bus frequency / &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF,t1modh&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Move decimal 255 into T1 modulo reg Hi (Free running timer)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; &amp;nbsp;#$FF,t1modl&amp;nbsp; &amp;nbsp; &amp;nbsp; ; Move decimal 255 into T1 modulo reg Lo&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #%00010000,t1sc0 ; Channel 1 Output compare, interrupt enabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH0 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH0 interrupts disabled until we are ready&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 MSxB, CH0 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 MSxA, CH0 Unbuffered output compare/PWM operation&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 ELSxB, CH0 Pin under port control initial output Low&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 ELSxA, CH0 Pin under port control initial output Low&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 TOVx, CH0 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 CHxMAX, CH0 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #%00010000,t1sc1 ; Channel 1 Output compare, interrupt disabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH0 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH0 interrupts disabled until we are ready&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 MSxB, CH0 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 MSxA, CH0 Unbuffered output compare/PWM operation&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 ELSxB, CH0 Pin under port control initial output Low&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 ELSxA, CH0 Pin under port control initial output Low&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 TOVx, CH0 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 CHxMAX, CH0 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; mov&amp;nbsp; &amp;nbsp; #%00010011,t1sc ; Start timer, no overflow int, div / 8&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 TOF, (no effect)&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 TOIE, (overflow interrupts disabled)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 TSTOP, (counter active)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 TRST, (Prescale and counter cleared)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bits 2,1,0 (Prescale for bus frequency / &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;But, I still have another problem. I have TIM2 set up as a free running counter with CH0 generating an interrupt every 100 uS. I use this to generate other time periods for my program. This works fine. I have TIM2 CH1set up for spark control,&amp;nbsp; similar to the TIM1 channels. The ISR routine is a bit more complicated because I have to enter it twice. First after a delay time to energize the coil and second to de energize it after the correct dwell time. I can't even get to the first interrupt. Again, I suspect my TIM2 timer set up. I've tried almost every combination I can think of but I only end up breaking the CH0 function. Here is how I have TIM2 set up:&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;; - Set up TIM2 as a free running ~1us counter. Set Channel 0 output compare&lt;/DIV&gt;&lt;DIV&gt;;&amp;nbsp; &amp;nbsp;to generate the ~100us(.1ms) clock tick. Interrupt vector "TIM2CH0_ISR:"&lt;/DIV&gt;&lt;DIV&gt;;&amp;nbsp; &amp;nbsp;Set Channel 1 output compare for spark control. Interrupt vector "TIM2CH1_ISR:"&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;MOV&amp;nbsp; &amp;nbsp; #%00110011,t2sc ; Stop Timer so it can be set up&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit7 TOF, Tim counter has not reached modulo value&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit6 TOIE, TIM overflow interrupts disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit5 TSTOP, TIM counter stopped&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit4 TRST, Prescaler and counter cleared&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit2 PS2, Internal bus clock / 8&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit1 PS1, Internal bus clock / 8&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit0 PS0, Internal bus clock / 8&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #$FF,t2modh ; Free running timer&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #$FF,t2modl&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #0T,t2ch0h ; Channel 0 high, 0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #100T,t2ch0l ; Channel 0 low, 100 = 0.1 ms @ 8.0MHz - DJLH&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #%11010100,t2sc0 ; Output compare, interrupt enabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH0 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH0 interrupts enabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit5 MSxB, CH0 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit4 MSxA, CH0 Unbuffered OC operation&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit3 ELSxB, CH0 Toggle output on compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit2 ELSxA, CH0 Toggle output on compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit1 TOVx, CH0 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ; Bit0 CHxMAX, CH0 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #$00,t2ch1h ; Channel 1 high, to be used for spark control&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #$00,t2ch1l ; Channel 1 low, 0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;mov&amp;nbsp; &amp;nbsp; #%00010000,t2sc1 ; Channel 1 Output compare, interrupt enabled&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 CHxF, CH1 output compare&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 CHxIE, CH1 interrupts disabled until we are ready&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 MSxB, CH1 Buffered OC/PWM disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 MSxA, CH1 Unbuffered OC operation&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 ELSxB, Pin under port control, initial output level low&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 ELSxA, Pin under port control, initial output level low&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 TOVx, CH1 No toggle on overflow&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 CHxMAX, CH1 No max duty cycle&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; mov&amp;nbsp; &amp;nbsp; #%00010011,t2sc ; Start timer&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit7 TOF, Tim counter has not reached modulo value&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit6 TOIE, TIM overflow interrupts disabled&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit5 TSTOP, TIM counter active&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit4 TRST, Prescaler and counter cleared&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit3 Unimplemented&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit2 PS2, Internal bus clock / 8&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit1 PS1, Internal bus clock / 8&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;; Bit0 PS0, Internal bus clock / 8&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;;***********************************************************************************************&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Any suggestions would be greatly appreciated.&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;Robert&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Sun, 10 Dec 2023 19:07:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1771832#M23821</guid>
      <dc:creator>roberthiebert</dc:creator>
      <dc:date>2023-12-10T19:07:22Z</dc:date>
    </item>
    <item>
      <title>Re: HC908GP32 Timer question</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1774119#M23822</link>
      <description>&lt;P&gt;Another update. After a lot of blood sweat and tears I think I have things figured out. Here is my TIM2 set up:&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%00110011,t2sc&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%FF,t2modh&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%FF,t2modl&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #0T,t2ch0h&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #100T,t2ch0l&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%11010100,t2sc0&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #$00,t2ch1h&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #$00,t2ch1l&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%00010000,t2sc1&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%00010011,t2sc&lt;/P&gt;&lt;P&gt;And for TIM1:&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%00110011,t1sc&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%FF,t1modh&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%FF,t1modl&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%00010000,t1sc0&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%00010000,t1sc1&lt;/P&gt;&lt;P&gt;mov&amp;nbsp; &amp;nbsp; #%00010011,t1sc&lt;/P&gt;&lt;P&gt;I'm still hunting bugs in the ISRs, but they appear to be functioning as they should.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 13 Dec 2023 17:30:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/HC908GP32-Timer-question/m-p/1774119#M23822</guid>
      <dc:creator>roberthiebert</dc:creator>
      <dc:date>2023-12-13T17:30:14Z</dc:date>
    </item>
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