topic Re: FEI Mode start time in 8-bit Microcontrollers

FEI Mode start time

Robinwithu — Tue, 15 Jul 2014 09:17:21 GMT

I am having a question Regarding the stabilization of internal Oscillator for MC9S08RN8 MCU.

I using using internal FEI mode and the default Bus frequency is 10Mhz and i am doing the changes in the ICS register to get 20Mhz.I would like to know that should i have to wait for certain amount of time after changing the ICS register till the Oscillator is stable (Internal Reference frequency and FLL) or MCU take care of itself and than it will execute the Rest of the code . please correct me if i am wrong , it will take maximum 1.3msec (300µsec for Internal reference clock and 1 msec for FLL)maximum time to generate stabilize clock.

Thank you n Kind Regards,

Robin

Re: FEI Mode start time

arpitaagarwal-b — Tue, 15 Jul 2014 11:29:25 GMT

Hello Robin,

You will have to wait till the clock will be stable.

For that, you need to poll LOCK flag in ICS_S register. It will set when the clock will be stable.

See the description:

Lock Status

Indicates whether the FLL has acquired lock. Lock detection is disabled when FLL is disabled. If the lock status bit is set then changing the value of any of the following bits IREFS, RDIV[2:0], or, if in FEI or FBI modes, TRIM[7:0] will cause the lock status bit to clear and stay cleared until the FLL has reacquired lock.

If this post helps you, kindly mark it as correct/helpful answer.

-Arpita

Re: FEI Mode start time

Robinwithu — Tue, 15 Jul 2014 12:10:58 GMT

Hi Arpit,

please see how i configured the FEI MODE

if ( NV_ICSTRM_INIT != 0xFFU)

{

ICS_C3 =NV_ICSTRM_INIT;

ICS_C4 =((NV_FTRIM_INIT) & 0x01U)

}

ICS_C1=0x04; // Default internal reference clock (39062.5 hz) to FLL(512) and FLL is generating ( 39062.5 X 512 = 20Mhz Khz )

ICS_C2=0x00; // BDIV = 00, Bus Frequency is 20Mhz / CPU Frequency is also 20Mhz

After this i did port initialization and the rest of the code .

is that correct?

in my case as u mentioned, i am not changing RDIV, IREFS or TRIM any register , the only thing what i am changing is BDIV . But still for safe side i can poll LOCK flag.

please tell me is the above code correct without Polling LOCK Flag?

Thanks n Kind Regards,

Robin

Re: FEI Mode start time

arpitaagarwal-b — Wed, 16 Jul 2014 04:23:09 GMT

Hello Robin,

If you are changing only BDIV, then polling of LOCK is not required as FLL clock will not be changed.

It is only bus frequency divider.

If this post helps you, kindly mark it as correct/helpful answer.

-Arpita

Re: FEI Mode start time

Robinwithu — Fri, 18 Jul 2014 07:58:31 GMT

Hallo Arpit

As you said "I need to poll LOCK flag in ICS_S register. It will set when the clock will be stable."

and i am pooling lock bit as follows in main loop

While (ICS_S_LOCK==0);

PORT_PTAOE==0x02,

PORT_PTAD==0x00,

While (1) {PORT_PTAD==0x02,};

But i am not getting any Output (high) on PORTA pin A1 but as soon as i poll for While (ICS_S_LOCK == 1);

the Output is available on PORTA pin A1.

But the code exit while loop when the condition is false which means it has unlock the FLL.

it's bit confusing for me.

please can you tell me what i am doing wrong?

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

Robinwithu — Fri, 18 Jul 2014 12:45:44 GMT

Hello arpitaagarwal-b37570,

In debugging mode the Default value of ICS_S=0x50 instant of 0X10; before doing any kind of debugging. is that correct ? or may be it's has already stabilized the Internal oscillator and that's why i am getting the FLL locked. or should i get the FLL locked after writing the default trim value and changes in BDIV reg.

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

Robinwithu — Mon, 21 Jul 2014 06:51:10 GMT

Hi arpitaagarwal-b37570 @Ankur kala

Please can you give me some solution or any kind of suggestion is also useful to find out the real problem.

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

Robinwithu — Mon, 21 Jul 2014 08:28:36 GMT

Hi iansmusical,

please can you help me with this topic.

Thanks and Regards,

Robin

Re: FEI Mode start time

arpitaagarwal-b — Mon, 21 Jul 2014 11:24:49 GMT

Hello Robin,

In debugging mode, LOCK status bit will be set only as it has crossed the chip start-up phase. And also, debugging can be performed after clock stabilization only.

So this observation is correct. As discussed earlier, changing BDIV should not change the lock status. In FEI mode, changing trim value will unlock the oscillator.

If this post helps you, kindly mark it as correct/helpful answer.

-Arpita

Re: FEI Mode start time

arpitaagarwal-b — Mon, 21 Jul 2014 11:27:50 GMT

Hello Robin,

In first case, when your code is hanged at the while loop, While (ICS_S_LOCK==0); read the ICS_S register value from the debugger window. Is the LOCK status 0 there??

Also, what is the code before this Lock polling lines? I am basically interested in knowing what changes you are doing for the clock.

-Arpita

Re: FEI Mode start time

Robinwithu — Mon, 21 Jul 2014 11:36:31 GMT

Hi Arpita,

Thanks for reply , please can you tell me than why code hanged here " While (ICS_S_LOCK==0) " as soon as i changed it to "While (ICS_S_LOCK==1)" the code work normal. but as we know that LOCK polling like this [ While (ICS_S_LOCK==1) ] is not correct.

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

iansmusical — Mon, 21 Jul 2014 12:30:47 GMT

Hi Robin,

I'm not sure if I can be much help but changing the BDIV can be done at any time and doesn't effect the FLL lock. Looking at the RN reference manual section 7.6.5 I see that changing the TRIM register will cause the lock status to be cleared until the FLL has reacquired the lock.

Guessing I'd have thought the lock would be obtained in standalone or debug mode because the internal clock is the default and must be locked to function!?

Thanks,

Ian

Re: FEI Mode start time

Robinwithu — Mon, 21 Jul 2014 12:55:28 GMT

Hi Ian,

Thanks for reply , yes BDIV doesn't have any effect and I am trimming it default value so their is no change in trim register.Try to find out myself what i am doing wrong.

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

Robinwithu — Thu, 24 Jul 2014 13:19:13 GMT

Hi Arpit,

Sorry for late reply.

I debugged the code and in debugging mode it works fine i.e. LOCK bit is 1 and the code is leaving the while loop [ While (ICS_S_LOCK==0); ] and further works as expected. But as soon as i flash the same code into MCU it doesn't work.i.e. The PORTA A1 pin does't go HIGH, as soon as i do the changes in while loop like this [While (ICS_S_LOCK==1);] the code works normal which means the PORTA A1 pins go HIGH.

Before the code i am having some variables and Trimming default value code which you send to me you can see the whole code as below.

I am not doing any changes in clock using all Default values except BDIV=0;

void main(void)

{

unsigned int tmp_uint; // zum kurzigen merken von intergern, zB FraState */

unsigned int tmp_timer; // Zwischenmerker für Zeitmessungen, bei Mindestlaufzeit und warten auf Dunkelphase */

DisableInterrupts;

if ( NV_ICSTRM_INIT != 0xFFU) { // 0xFF6FU Test if the device trim value is stored on the specified address

// ICS_C3 = *(uint8_t*)0xFF6FU; // Initialise ICS_C3 register from a non volatile memory

// ICS_C4 = (uint8_t)((*(uint8_t*)0xFF6EU) & (uint8_t)0x01U); // Initialise ICS_C4 register from a non volatile memory

ICS_C3 = NV_ICSTRM_INIT ; // This Registers are not Define in Derivative.h file thats why we have to define this Environment Variable before the start of code

ICS_C4 = ((NV_FTRIM_INIT) & 0x01U); // Trim the internal clock :((NV_FTRIM_INIT) & 0x01U);

}

ICS_C1 = 0x04; // internal reference clock to FLL and FLL is generating 16000-20000 Khz ; Ref. Freqeuncy is set at 31250-39250 Hz * 512 = Appx.16-20 Mhz

ICS_C2 = 0x00; // BDIV = 00, Freq is now 16-20Mhz

while (ICS_S_LOCK==0){;} // [0] FLL is currently unlocked, [1] FLL is currently locked.

PORT_PTAOE = 0x02; // PORTA pinA1 Output enabled

PORT_PTAD = 0x00; // Initialise PORTA1 pin

while (1) {PORT_PTAD = 0x02;} // Set PORTA1 pin in forever loop

}

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

Robinwithu — Thu, 24 Jul 2014 13:20:42 GMT

Hi Arpit,

is their any issue with compiler code optimization ?

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

Robinwithu — Fri, 25 Jul 2014 07:31:34 GMT

Hi arpitaagarwal-b37570,

I found the problem which is as follows , After disassemble the code what i found at BEQ instant of BNE.can you explain me what exactly it does with BEQ n why?

does it has something to do with Code optimization ?

0000E0A8 A604 LDA #$04

0000E0AA C73038 STA $3038 ; ICS_C1

-----------------------------------------

0000E0AD 4F CLRA

0000E0AE C73039 STA $3039 ; ICS_C2

-----------------------------------------------------------------------------------------------------------------------------

0000E0B1 C6303C LDA $303C ; ICS_S

0000E0B4 A540 BIT #$40 ; wenn Lock = 1 bleiben Sie in der Schleife !, das ist ein BIT Test !

0000E0B6 27F9 BEQ *-5 ;abs = $E0B1

-----------------------------------------------------------------------------------------------------------------------------

0000E0B8 A602 LDA #$02

0000E0BA C730B0 STA $30B0

0000E0BD 3F00 CLR $00

0000E0BF 6E0200 MOV #$02,$00

0000E0C2 20FB BRA *-3 ;abs = $E0BF

Thanks N kind Regards,

Robin

Re: FEI Mode start time

iansmusical — Fri, 25 Jul 2014 07:53:59 GMT

Hi Robin,

The assembler code makes sense to me. It loads the ICS_S register into A and carries out a bit test at position 0x40 and crucially the BEQ says if bit position 0x40 is set in ICS_S then check again. If the BEQ was a BNE then the opposite would happen, it would exit the loop.

Thanks,

Ian

Re: FEI Mode start time

Robinwithu — Fri, 25 Jul 2014 08:04:53 GMT

Hi iansmusical

Thanks for reply. Actually i just found one problem , in while loop when i am comparing while (ICS_S_LOCK==0){;}, so in this case After stabilization of internal oscillator LOCK bit will set to 1 which means in assembly code it should be (BNE) branch if not equal but it's giving me BEQ in assembly code .why i don't know? or am I understanding it wrong?

I am expecting that it should leave the while loop (After making sure that FLL is locked) but it doesn't.

BEQ= branch if equal

BNE= branch if not equal

Thanks and Kind Regards,

Robin

Re: FEI Mode start time

iansmusical — Fri, 25 Jul 2014 10:32:27 GMT

Hi Robin,

Yes your assumption is correct that the while loop will exit when the lock bit is set to 1 because you are saying while ICS_S_LOCK is equal to 0 loop and check again.

The resultant assembler is also correct in using BEQ because you are saying branch or check again if ICS_S_LOCK is still equal to 0. When ICS_S_LOCK becomes 1 the BEQ condition will not be met as the "== 0" part is no longer fulfilled.

Thanks,

Ian

Re: FEI Mode start time

Robinwithu — Fri, 25 Jul 2014 11:12:08 GMT

Hi Ian,

Actually i debug the code and found that LOCK bit is = 1, which means that the code should leave the while loop but when i am flashing the code in MCU it doesn't go further and as soon as i changed the while(ICS_S_LOCK==1) it work fine , that's why i am wondering , is it BEQ correct or it should be BNE? cause BEQ says that Branch if Equal , for my understanding if the condition is matched than do the branching or exit the loop. isn't it so? n in my case it should exit the loop only in case when the condition is false.

Thanks n Kind Regards,

Robin